You're quite right, the registers for the DMA chip's actions are indeed within the MMU. I don't think that matters conceptually, but it's technically correct.
BW
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You're quite right, the registers for the DMA chip's actions are indeed within the MMU. I don't think that matters conceptually, but it's technically correct.
Btw, you can make writes to ST-RAM faster as well. You don't wait until the slow write bus cycle at ST-RAM completes, you post it (or them) and they would complete in parallel while the CPU is accessing fastram (which would happen all the time if you shadow whole RAM).agranlund wrote: ↑Tue Dec 08, 2020 12:38 am
Writes to ST-RAM cost the same as before but reads end up being super fast
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You would basically be trading fast reads from screen memory to instead get fast writes to work memory so I guess it's a matter of where the bottleneck lies in each particular game. Updating the screen usually involves a ton of read-modify-writes so it's a bit of a guess really.
I do!