The TF1260 is broadly designed to have a ram and clock controller on one CPLD and the insanity of the 3-state machine bus translator on doing all the databus translation on the other one. By default all accesses go to the Amiga via the bus cpld unless the ram cpld spots its something it should handle and flags that to the other one. Simple eh? Well at 25Mhz it is. Still not too rough at 50mhz.. at 100Mhz its more complex... let me explain.
The sequence is something like..
1. 68060 asserts TS for 1 clock period along with address.
2. RAM CPLD decodes this address as something it needs to handle and asserts INTCYCLE (an interconnecting signal between the two).
3. BUS CPLD sees INTCYCLE and knows do stay idle.
4. RAM CPLD handles the request and asserts TA.
Still seems simple.... but look at this..
- Screenshot 2021-12-19 at 01.02.06.png (75.99 KiB) Viewed 2372 times
Add to this the fact that power consumption squares with CPU speed and that power is always dissipated as heat. I dont have graphs for what happens to the setup times for the Xilinx CPLDs as the temperature goes up but i would assume they go up as do the chances of a bitflip.
In short writing firmwares for this stuff isnt like writing a computer program. You need to understand high speed signal propagation in different frequency regimes. Its not like writing simple 68k assembler or C.
And yes i know some of this is solved in FPGA. But we get 5V to 3.3V buffering for free with these CPLDs so we are able to cost reduce the whole thing. FPGAs add their own issues. They need more power supplies, serial eproms, flashing infrastucture. All this increases cost. Oh and if you want to have enough IO pins you need 2 of them or BGA... kiss goodbye to hand soldering then.
