The ATTINY is being used as a flash register, so it will store the settings until changed..troed wrote: Fri Nov 24, 2017 7:43 pm Will the ATTINY store in its flash and copy to sram when booting, and then any changes made during regular use & reset will only touch the sram?
Truetroed wrote: Fri Nov 24, 2017 7:43 pm Reason for asking is that my use for the 8/32MHz register would be to run devpac and compiling in 32MHz and switch to 8MHz when launching the code. Rewriting the flash all the time will quickly wear it out ...![]()
Saying that, there was a bit of trickery involved with all this... Because basically the CPU writes to the PLD internal registers, and writes the values to the ATTINY at the same time.
I guess I could use another data line direct from the CPU as a switch line to actually only update the PLD register, or the ATTINY register..
So maybe use data line 9, if high then write to the ATTINY (will also write to the PLD internal latches), and when low, just update the PLD internal latches... This way you can actually configure the booster on/off without having to write to the ATTINY each time
I don't follow you there I think...troed wrote: Fri Nov 24, 2017 7:43 pm (This of course puts additional requirements on the clock cycle change to be made crash-safe which might be too difficult .. ?)
The 32MHz/8MHz switch can generally happen at any time... If you looked at the CPU clock signal on the scope, you would see it changing between 32MHz and 8MHz constantly anyway...
