Atari ST OPL3 cart schematics

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nokturnal
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Atari ST OPL3 cart schematics

Post by nokturnal »

Hi, I've 'finished' schematics for Atari ST OPL3 cartridge. Is there anyone experienced in ST hardware design, who could take a look at it and review it? It is my first project that big and I'm still learning. I'm not sure about decoupling capacitors connections and not sure if +5V from cartridge can drive all of these. I'm currently preparing pcb for it and plan to produce small batch depending on prototype. If anyone has any suggestions then fire away.
My main concern with decoupling capacitors should have output (I think) output to VCC, GND pins on the right side(it's load) and power input +5V, global GND on left side. Something like this:
Decoupling capacitors
Decoupling capacitors
Decoupling_caps.png (6.95 KiB) Viewed 2008 times
Current state I've looked up on resound opl3 adlib card, but I'm not sure it's correct..
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AtariStOpl3Cart.pdf
Atari ST OPL3 cart schematics v.3
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sporniket
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Re: Atari ST OPL3 cart schematics

Post by sporniket »

Too bad there is no sample schematics in the datasheet of the OPL3.

About decoupling capacitor, personnally I took the habit of putting them next to the target IC and wire the "+" side to VCC, at the price of requiring more space on paper.
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Re: Atari ST OPL3 cart schematics

Post by stephen_usher »

Every chip should have a decoupling cap as close to VCC as possible. These days I use surface mount caps on the other side of the board, which saves space on the "component side".
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nokturnal
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Re: Atari ST OPL3 cart schematics

Post by nokturnal »

@sporniket: Yes, there are only sample integrations with dedicated DAC (2 channels and 4 channels). I'm thinking about 4ch variants too, but I would like to do first version right.
@stephen_usher: thanks for a tip. Yes, I'm aware that decoupling caps should be as close to VCC as possible. I'm still working on PCB layout, this will take a while. In general I will be adding those decoupling capacitors to every IC, near Vcc. That is the plan..

edit: @sporniket: I'm attaching update with added all decoupling caps on all ICs.
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AtariStOpl3Cart.pdf
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saulot/[nokturnal]
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nokturnal
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Re: Atari ST OPL3 cart schematics

Post by nokturnal »

I've made initial pcb design prototype. Based on above schematics. Any feedback welcome. Anyone could share some hints how to test everything before actually connecting this thing and not burning ST internals (like MMUs)? :lol:
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nokturnal
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Re: Atari ST OPL3 cart schematics

Post by nokturnal »

I've made some changes to development pcb. I've shortened length a little and added pinouts for OPL3 interface hardware debugging.I hope to get some more feedback/review before I send it for manufacturing.
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Badwolf
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Re: Atari ST OPL3 cart schematics

Post by Badwolf »

nokturnal wrote: Sun Mar 24, 2024 5:24 pm I've made some changes to development pcb. I've shortened length a little and added pinouts for OPL3 interface hardware debugging.I hope to get some more feedback/review before I send it for manufacturing.
I'd like to offer some help, but I'm not an audio guy and know little about what's needed on that front.

One thing I might suggest is you include some mounting holes, however. This is a long cart and will flap around a bit. If you'd like to put it in a case later, a few 2.5 or 3mm holes at appropriate places might assist!

BW
DFB1 Open source 50MHz 030 and TT-RAM accelerator for the Falcon
DSTB1 Open source 16Mhz 68k and AltRAM accelerator for the ST
Smalliermouse ST-optimised USB mouse adapter based on SmallyMouse2
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nokturnal
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Re: Atari ST OPL3 cart schematics

Post by nokturnal »

@BadWolf It would be really awesome. I'm also not audio guy, I'm even not an electrician ;).. I'm aware that there's no mounting holes, but I'm treating this board as a first prototype/development version (I will do max 5pcs of it) to verify if everything works as intended and add drivers support(which should be easy in comparison to other similar devices). Final version will be smaller as I want to get rid of THT elements and I'm considering adding another output with volume (not sure about it).

I think more experienced people will look at it the better. I've got already some feedback issues related to pcb, which I would like to address in next version. Currently I'm mostly worried about physical pcb and issues related to power connections and decoupling capacitors, so if you could take a look if there is something horrible there then it would be great (less probability that I will burn something). I can send you link to my repository if you would like to help.
Atm the things which I need to fix in next version are:
1) schematics, rework of A0 signal passed to latch. Probably accessing odd address will end badly on plain m68k, so I had an idea to replace it with whole word access check by checking if both UDS/LDS are low (I guess when we will want read 16bit word from given address).
2) pcb, remove throughole vias from SMT element pads.
3) Fix cartridge edge connectors, probably there will be some issues with it on some Atari models.
4) Got suggestion to replace 74LS343 with 344 version.

So if notices/knows something that could backfire. Tell me, please :)..
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Re: Atari ST OPL3 cart schematics

Post by Badwolf »

nokturnal wrote: Tue Mar 26, 2024 5:01 pm I think more experienced people will look at it the better. I've got already some feedback issues related to pcb, which I would like to address in next version. Currently I'm mostly worried about physical pcb and issues related to power connections and decoupling capacitors, so if you could take a look if there is something horrible there then it would be great (less probability that I will burn something). I can send you link to my repository if you would like to help.
In terms of caps, it seems vastly over spec'd to me -- none of my boards have had any electrolytic bulk caps on them. Admittedly I don't see electrolytics on your picture, but they're in the schematic. Looks like you've converted them to MLCCs in layout. My boards are all (bar one) digital, so it's a bit different, but still:

For example, you have 7 decoupling caps on what appears to be a fully digital-side quad NAND gate. One 100nF MLCC cap should be enough for that, I'd have thought.

100nF, one per power pin on each chip. As close to that pin as you can get them. Try to have as big an unbroken ground plane as you can somewhere on the design -- either try to get all your data tracks on the top side or a four layer board. You're dealing with audio. Ground layer is very important.

Now where you probably *do* want bulk electrolytics would be on the audio in and out sections, but I don't see much there. That might be worth looking into some example layouts. The diagram here looks pretty typical to me:- https://www.eevblog.com/forum/projects/ ... #msg727343

Also you've got dual sided load. Whilst that's fine for a prototype, if you'd like the board house to assemble all the fiddly bits, keep them all one one side if you can. It'll save you mucho pesos down the road.
Atm the things which I need to fix in next version are:
1) schematics, rework of A0 signal passed to latch. Probably accessing odd address will end badly on plain m68k, so I had an idea to replace it with whole word access check by checking if both UDS/LDS are low (I guess when we will want read 16bit word from given address).
Now I should point out at this point, I'm not familiar with the project so apologies if any of these questions are dumb:-

Are you working from an existing design? If not I wouldn't bother with A0 at all. Why'd you need it?

You're actually not even connected to the data lines so any read you do will return 0xFF for a byte access and 0xFFFF for a word access. I assume this a 'write only' design and you don't need any information back.

If you aren't working to an existing driver and trying to keep compatibility, drop A0, use A1 and up. You've got five unused address lines without trying to synthesise another one.

In fact, why are you using the latches anyway? Is there a minimum hold time on the YM262's data in? If not, just have ( UDS | ROM4 ) connected to CS and WR.

You can use your quad NAND for that, if you want: https://en.wikipedia.org/wiki/NAND_logic#OR
3) Fix cartridge edge connectors, probably there will be some issues with it on some Atari models.
I've got a Kicad cart edge library embedded in one of my projects somewhere. Let me know if you'd like it.

Helps to chamfer the edges of it with a file, but they do work fine if you're gentle.
4) Got suggestion to replace 74LS343 with 344 version.
373s (latches) and 374s (flipflops) trigger on the opposite edge -- be careful you know what you want here. I'm not 100% sure ROM4 will actually fully deassert on a back-to-back read either.

Sorry I can't be of more use without knowing a bit more about it!

BW



PS: I switch my schematic page sizes to A3. Gives you much more space and is still readable when printed out on A4.
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nokturnal
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Re: Atari ST OPL3 cart schematics

Post by nokturnal »

@badwolf If it comes about audio part I didn't invent it. I've just saw existing design Resound OPL3 card schematics and adapted everything as best I could. Maybe I've misinterpreted some parts of drawings (they look ambiguous especially in decoupling caps parts) and/or there were some parts fixing additional issues on ISA interface, which will not apply to ST cartridges, like +12V/-12V power rails.
They have used filmic capacitors to reduce noise on the board, there's no electrolitic caps (I probably will add them, but couldn't find proper footprint in KiCad). Some Sound Blasters had problems with noise on output and it seems that this card is quitest of them all. Here is link and schematics (there's no pcb project I could look on). Hard to tell how many layers they have used. I like this form factor and if I could achieve similar result for ST cartridge it would be great. Reset circuit and clock generation I think I've took from 8-bit opl3 cartridge by TOri(Yamari, which can read/write opl3 state btw) or OPL2 sound board, I don't remember.

So I've taken audio parts (OPL3 Resound 2 channel mode, there is also posibility to make 4 channel / surround output it's based on opl3 documentation by Yamaha, but for some reason no one has picked up this design in pc sound blaster cards, it would be cool to create this variant too btw) and I've added interface which is my 'invention' after lecture of old articles.
And why latches? Well I've done some research and I've looked through those old articles 1 2 and I've seen some videos about latching address lines and this looked like something I could use. I've ditched reading from opl3, because it wasn't needed in all opl3 devices I've programmed previously.
Need for this latch was purely to save state of adress lines to have certain pattern set on OPL3 data / address lines, after setting this I need to (assert /WR low or high OPL3 for certain time to set either address to which I'm writing data and next the value). Timings are different for data and address setting and depend on m68k cpu speed (because point of reference is always opl3 clock, OPL2 has slower clock and writes take more time for instance, which is not true on opl3). There are also some different wait states after writing opl3 address and opl3 data (we need to hold /WR for certain number of opl cycles). I also wanted to have an option to add second opl3 chip, that's why on second latch there are some unconnected signals, one is reserved for selecting opl3 unit (0/1) (like in opl3 duo).

Regarding your NAND remark I need some time to digest your idea, if it could remove need of latches it would great (one part out, less space). I've considered use of NAND gate, but for different purpose i.e using byte/word read to set /WR to high/low by wiring output of the NAND gate to UDS/LDS lines, so if UDS/LDS would be low(16 bit read attempt), then it we would set WR to low, in other cases (like byte read) it would be set to high. So, sequence would be like WR high(on init), set data/address bits, set /WR to LOW state, set WR to HIGH state (we usualy set opl3 address, next opl3 data). I'm not very sure if it would work the way I think (need to make reality check with logic analyser I guess). But maybe existing solution will be good enough as long it will not trigger address / bus error on m68k cpu.

Here is sample, which TOri has sent me (with A0 taken from LDS (,which is active low) and is our /WR strobe):
We want to set $01 adress register YM262 (A0=0, A1=0) - LSI TEST (Array 0)
1. We read back from #$FA0101 to d0, this will set 01 - data, 01 - adress (H - /WR) on latches
2. We turn off /WR by clearing /WR to 0 - low state
3. (we idling if needed)
4. We turn on /WR by setting /WR to 1 - high state
We need to repeat similar procedure to write to previously selected OPL3 address some data..

I don't have existing solution yet (there's no working drivers yet, but I've got some inspiration from OPL2 cartridge code made by Insane/TSCC some years ago, but I haven't seen no cartridge or schematics). After fiddling with several devices that use OPL3 chip (centronics/usb/spi) I came to conclusion that there should be something simpler and quicker way to write to OPL3 (from all of them OPL3LPT was the best, but printer port handling is awkward and there's missing signal on STs, which cripples OPL3 to OPL2, the only plus are reduced wait states).

Keeping separate planes for audio and rest is a good point, I'm aware of this issue, but I'm not sure if I can execute it properly. Maybe with some guidance I could make version with ground plane separation. I also didn't know that placing small elements on one side is cheaper when manufacturing, currently I'm ready to solder everything by hand (at least for first prototypes). I will be certainly planning next steps, when I will have working prototype and drivers (which should be much easiest than for other devices, of course if machine will be alive after inserting carrtridge :D). And I would like to make proper cases and labels for it to make it more like 'real thing'. I'm not a fan of dangling pcbs from cartridge port.
Thanks for pointing out your edge connector and eev links, I will check everything out.
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