dml attempts a Raven

[dml]

Hoho - almost a trap!

Presumably its ok to use a 20-pin ATX supply, in the 24-pin socket, so long as it's seated towards the correct end? Normally this is ok and the pins are keyed anyway.

Still... the seatbelts are off

[dml]

Ok so I went ahead with the 20pin ATX and after some confuse regarding the power button on the Raven and the ATX missing a fan - so it appeared not to do anything when powered on - I have made some successful measurements.

I did this with the big ATF chip removed since they're annoying to source if something went wrong.

power.jpg (654.02 KiB) Viewed 33 times

I'm seeing:
- no flames (!!!)
- 5v on the 5v headers
- 3.3v on the 3.3v headers
- 24MHz on the SMD oscillator I was concerned about being backwards
- 48MHz on the main oscillator

trace.jpg (209.42 KiB) Viewed 33 times

Some of the chips are getting warmish but nothing unusual. The MFPs and the GALs mainly.

I'm not seeing the clock on the CLK pin of the 060 socket - I guess that's because Nessi is missing and the signal routes through there?

Anyway I feel a bit more confident now about proceeding with the ATF programming step.

[PhilC]

Good luck starting off at 96mhz. Hoping your chips are fine at 48.

[dml]

Ok after some time with the schematic, I can see PCLK->CLK:060 is controlled by J102, which I have left open. That explains why I didn't see activity on the PGA socket.

[dml]

Good luck starting off at 96mhz. Hoping your chips are fine at 48.

I did manage to obtain a 40MHz oscillator after a bit of a wait and made sure there is a socket so if things go badly I should be able to swap it

[agranlund]

Wohoo! ATF's and MFP's getting a bit warm sounds normal to me.

If you jumper J102, J104 and J105 to the topmost positions you should be getting a valid the PCLK signal on the CPU socket.
(You will need Nessi for the CLKEN signal though)

Screenshot 2025-07-04 at 20.56.09.png (1.61 MiB) Viewed 26 times

[dml]

Thanks! I had almost figured that out but not quite I could see 48Mhz on J102 but was looking at J104 to see how it gets involved.

I'll set up the jumpers and see how it looks.

[dml]

So with this config, I don't see anything on the CPU socket.

I do see 48MHz on the innermost pin of J102 (the not-jumpered pin) but nothing on the jumpered pair.

[dml]

Correction!

I do see 96MHz on the CPU socket, just at a lower voltage range - my trigger was not set correctly for it so it just became noise in this scope's digital mode.

[EDIT]

The CLK signal at the CPU is about 1.3v pk-pk which seems quite low, is that normal?

[agranlund]

The CLK signal at the CPU is about 1.3v pk-pk which seems quite low, is that normal?

I'm far from an expert on it, but I think that's likely due to the fast signal for the oscilloscope and/or probes.
My 50mhz, 500MSa/s starts acting the same but already at lower frequencies.