Blitter may still be used for ST-RAM to ST-RAM work and, if using AltRAM.PRG (rather than AltROM.prg) from ROM to ST-RAM.User wrote: Greetings Badwolf,
Congratulations for th excellent research you performed!
If you let me, I have some questions regarding the accelerator,
-Can the blitter be used for games or other things with the accelerator being used at 16 MHz?
I don´t mean to use the on board fast RAM, I want to use the blitter and DMA audio with the common ST-RAM.
I'm looking at whether BLITFIX.PRG may be modified to make this simpler.
I also hope that, given time, the blitter can be made to work reliably in all modes.
The primary distinctive element of this booster is that it does indeed use SDRAM and hence requires controller logic. The aim is for the lowest price. When available(!) the CPLD + SDRAM is usually much cheaper than a smaller logic chip and SRAM.-You are using DRAM, that requires refreshing circuit and logic... is the CPLD being used for this purpose?
Personally I own plenty 2Mx16bit SRAM chips, where the refreshing need can be avoided at all.
Can be the accelerator simplified in order to discard the CPLD, via using SRAM, and add some standard logic chips to detect when the CPU is accesing the ST-RAM bus?
An SRAM-based AltRAM acclerator would be much simpler and could potentially be much faster. Exxos has his SEC booster under development, for example. This will be a much more impressive board, but the trade-off is cost.
There would be little point reworking this booster into an SRAM board as this is a booster build around SDRAM.
The CPU runs at 16MHz whenever it's not accessing the ST motherboard (where it switches down to 8MHz). Non-ST-RAM instructions and AltRAM access is therefore accelerated.-I suppose the accelerator uses 16 MHz for instruction execution, but 8 MHz for bus access, is this correct?
Thanks in advance,
Regards,
BW