Flashy Clock - Yet another DEV board

[exxos]

I think I have worked out what is going on with the diode now.. The problem is the buffers supply is done via a 100K resistor charging up a 100nF cap... Basically takes a long time..

So I thought, lower the resistor to 10K.. nope... 1K nope... 100R.. booted but back to wrong banks again... In that case the resistor was putting a lot of current through the diode and long story short, it ended up with a 1V drop across it so it was not disabling the buffers any more

Then I decided just to un-solder the 100nF cap. And lo and behold, I can now switch TOS banks again!

As to why this problem only showed up this week when it never did on any of the other machines is beyond me

I really need to find some better solution for this as I wanted to remove the buffers for the 3.3V version.. But now it seems I will have to keep one to isolate the bus And add a load of pull-up resistors Which then means it yet another re-spin of the board

I did wonder about just adding a tri-state inverter onto the H5 to solve the problem on the motherboard itself.. But then flashy clock would not be usable on original machines, and if this problem happens with the DMA, it could well happen with some other chip or some other add-on in the future.. So I don't want to really excess problem on the motherboard itself... Not only that it would render flashy useless on all previous other motherboards as well So this problem has to be solved on flashy clock itself..

I will keep thinking about it to see if I can conjure up some other workaround or solution to the problem...

[exxos]

It seems 100K and 100nF takes forever to charge, but even downgrading to 390pF still takes too long to charge.. But down to those values I end up with about 0.5V ripple on the buffer supply So instead of messing around with the capacitor I thought I would just 0V is Vref pin instead... But annoyingly that also discharges the capacitor

This should have been the last revision of the board, Then the GLUE throws a huge curveball yet again So the only way to solve this would be to actually add a bus isolated chip on the board which means another board re-spin

EDIT:

Another idea, is maybe I can charge the capacitor directly off the PLD bypassing the 100K resistor to "quick charge it"..hmmm

EDIT2: Don't think the PLD has enough jungle juice to charge the cap fast enough

[exxos]

New new new idea

Idea is to not let the capacitor charge up in the first place, and only allow it to charge after reset has completed.. The problem is there is still the problem of charging it up fast enough...

So currently what seems to have made it work, is to hold the capacitor to 0V during reset.. After flashy as updated its registers,the PLD then switches to charge the capacitor from the PLD at 3.3V... Then when the voltage reaches whatever the threshold voltage is on the PLD, probably about 2 V.. to turn off the charging and let the voltage settle on the cap "naturally".. 2V on the buffers seems to work..

so the charge cycle looks like this...

IMG_6195.JPG (65.81 KiB) Viewed 4951 times

0 volt
rapid charge to 2V
charge off

It is actually using a 10K pullup.. which isn't great as it causes voltage offsets on the buffers.. so when I swap back to 100K and bet it breaks as it would take a LOT longer to charge the cap.. but will see....

EDIT:

Back to 100K..

note the timebase WAS 1ms and now 5ms..

You can see the sharp rise up to about 2 V, then the PLD isolate then lets it charge naturally.. probably takes like 20ms to get the bulk of the charging done...

IMG_6196.JPG (65.21 KiB) Viewed 4951 times

EDIT2:

The cap charge time looks to be 100us, so the PLD must be outputting about 3mA

[exxos]

A bit neater, and working correctly now

IMG_6198.JPG (402.63 KiB) Viewed 4911 times

IMG_6199.JPG (386.89 KiB) Viewed 4911 times

Very easy to program new banks, just load the ROM file and away you go!

[Icky]

Finally with all the testing, changes and bug fixes @exxos and I have been making on the Flashy Clock board have culminated in the Flashy Clock v7.0.

Testing on the previous version has been good and the board functions well with its features of 8MB ALT-RAM, 4x FlashROM banks and RTC.

We have just sent off for new boards to be made that fit the H5 3V3 bus. I had a bit of a hiatus from PCB layout which stalled the effort as normal (there is no such thing as normal) life and work have been getting in the way.

As a preview this is a render of the Flashy Clock v7

Screenshot 2021-04-09 at 14.46.40.png (299.68 KiB) Viewed 4721 times

Screenshot 2021-04-09 at 14.47.28.png (317.35 KiB) Viewed 4721 times

[exxos]

Great work @Icky

[DoG]

I need one now @Icky . Nice job.

[exxos]

V7 I might add is 3.3V only.. Will only work in the H5 type boards with a 3.3V bus. Though we are contemplating a adapter board so they can be used on 5V based boards. But I'm not sure when those boards will get done, it depends on interest overall.

Also V7 will be compatible with the SEC booster. That project was stalled deliberately this time because the ROM is "stuck" at 32MHz speeds. V7 will allow the SEC to run ROM full speed (64Mhz etc). Once these have been matched up and working then finally I can bring to a close the fastest 68000 booster which can be made using original silicon.

The 8MB alt-ram is difficult to find faster than 55ns (I think @Icky ? ) But still that should be fast enough to give a speed boost up to effectively 32Mhz anyway.

[Icky]

The 8MB alt-ram is difficult to find faster than 55ns (I think @Icky ? ) But still that should be fast enough to give a speed boost up to effectively 32Mhz anyway.

Yep, 55ns was the fastest we could source for that form factor. Anything less than that was non-existent.

[Seabassnash]

I've been desperate for one of these!