# Atari ST Blitter - cell pin definitions
# Recovered from ASICs-new.zip. Each entry cites its evidence.
#
# SECOND.LIB is Atari's Silos behavioural library (/ASIC/LIB/SECOND.LIB) and gives
# both pin order AND internal logic for most sequential cells - use it to write the
# Verilog primitives rather than deriving them by hand.
#
# Convention: an X prefix marks the complement rail (XQ, XC, XR). Cells emitting both
# rails are dual-rail drivers, not inverters. In Verilog, transliterate literally and
# let synthesis collapse the redundancy.

# ================= RESOLVED =================

BITBLT    O D E H H0 H1 M O0 O1 O2 O3 XD XE XS
          [dangling/sub-wiring]
BLTAD1    CO DO O D DI DS E II L S SD XD XE XL XS
          [dangling/sub-wiring]
BLTADD    CO DO O CI D DI DS E II L S SD XD XE XL XS
          [dangling/sub-wiring]
DDL1      Q XQ C1 C2 D1 D2 XC1 XC2
          [dangling/sub-wiring]
FF1       Q XQ C D XC
          [SECOND.LIB]
FF2       Q XQ C D XC XR
          [SECOND.LIB]
FF4       Q XQ C D XC XS
          [SECOND.LIB]
I1        O A
          [GATEREF.LIB]
I10       O A
          [GATEREF.LIB]
I12       O A
          [GATEREF.LIB]
I15       O A
          [GATEREF.LIB]
I2        O A
          [GATEREF.LIB]
I3        O A
          [GATEREF.LIB]
I4        O A
          [GATEREF.LIB]
I6        O A
          [GATEREF.LIB]
I8        O A
          [GATEREF.LIB]
I9        O A
          [GATEREF.LIB]
IP        I
          [GATEREF.LIB]
IP1       O I
          [dangling/sub-wiring]
IP2       O I
          [usage + IP1 confirmed as O I]
IPAD      I
          [usage: only ever external input nets (CLK, XRES)]
L1        Q XQ C D XC
          [SECOND.LIB]
L2        Q XQ C D XC XR
          [SECOND.LIB]
LSDCA     CO Q XCO XQ C D L XC XL
          [dangling/sub-wiring]
LSDCB     CO Q XQ C CI D L XC XCI XL
          [dangling/sub-wiring]
LSDCC     CO Q XQ C CI D L XC XL
          [dangling/sub-wiring]
LSDCD     Q XQ C CI D L XC XL
          [dangling/sub-wiring]
LUDCA     CO Q XQ C D DN L UP XC XL
          [dangling/sub-wiring]
LUDCB     CO Q XQ C CI D DN L UP XC XL
          [dangling/sub-wiring]
LUDCC     CO Q XQ C CI D DN L UP XC XL
          [dangling/sub-wiring]
LUDCD     Q XQ C CI D L XC XL
          [dangling/sub-wiring]
MAND      O A B C
          [GATEREF.LIB]
ML1       Q TQ XQ C D E XC XE
          [SECOND.LIB]
ML2       Q TQ XQ C D E XC XE
          [dangling/sub-wiring]
NA2       O A B
          [GATEREF.LIB]
NA3       O A B C
          [GATEREF.LIB]
NA4       O A B C D
          [GATEREF.LIB]
NA5       O A B C D E
          [GATEREF.LIB]
NA6       O A B C D E F
          [GATEREF.LIB]
NA8       O A B C D E F G H
          [GATEREF.LIB]
NO2       O A B
          [GATEREF.LIB]
NO3       O A B C
          [GATEREF.LIB]
NO4       O A B C D
          [GATEREF.LIB]
NTR       D G S
          [GATEREF.LIB]
OB        O I
          [SECOND.LIB (NOB body: OB O XI)]
OB2       O N P
          [SECOND.LIB (NOB2 body: OB2 O N P)]
OPAD      O
          [usage: only ever external output nets (A23, A11)]
RSDCA     CO Q XCO XQ C D L R XC XL XR
          [dangling/sub-wiring]
RSDCB     CO Q XQ C CI D L R XC XCI XL XR
          [dangling/sub-wiring]
RSDCC     CO Q XQ C CI D L R XC XL XR
          [dangling/sub-wiring]
RSDCD     Q XQ C CI D L R XC XL XR
          [RSDCC minus CO; same drop-CO pattern proven on LSDCC/LSDCD]
SAB       O A B SA SB
          [GATEREF.LIB]
SC2A      CO Q XCO XQ C XC XR
          [SECOND.LIB]
SC2B      CO Q XQ C CI XC XCI XR
          [SECOND.LIB]
SC2C      CO Q XQ C CI XC XR
          [SECOND.LIB]
SC2D      Q XQ C CI XC XR
          [SECOND.LIB]
TS1       O E I XE
          [SECOND.LIB]
TS5       N P E I XE
          [SECOND.LIB]
XO        O A B
          [GATEREF.LIB]

# ========== AND-OR-INVERT GATES ==========
# Form: O = ~( AND-term | AND-term | ... ). Inputs appear in term order.
# The pin COUNT is certain; the grouping into AND terms is graded below.

AN12      O + 12 inputs  -> 4 terms x 3 inputs
          PROVEN: groups are (O3,selA,XD)(O2,selA,D)(O1,selB,XD)(O0,selB,D) - the BITBLT op selector
AN15      O + 15 inputs  -> 5 terms x 3 inputs
          LIKELY: 15 inputs split cleanly into 5 groups of 3
AN6       O + 6 inputs  -> 2 terms x 3 inputs
          LIKELY: 6 inputs split cleanly into 2 groups of 3
AN17      O + 17 inputs
          UNCERTAIN: 17 inputs, does not divide evenly; probably 3+3+3+3+3+2
AN2       O + 4 inputs
          UNCERTAIN: 4 inputs, appears to be 3+1
AN1       O + 3 inputs
          UNCERTAIN: 3 inputs, appears to be a single 3-input term
