ST Blitter (4051) - AND-OR-INVERT primitives needed from pri150ww.lib
=====================================================================

WHAT THIS IS
The Atari ST Blitter, reverse engineered from Atari's own netlist. Everything
is recovered except the internal grouping of a few AND-OR-invert (AOI) gates,
which were defined in a Silos primitive library (pri150ww.lib) that is missing.
The gates are AN1, AN2, AN6, AN12, AN15 and AN17.

WHAT AN AOI GATE IS HERE
Each is a single output AOI: O = NOT( term OR term OR ... ), where each term is
an AND of some inputs. In the netlist the inputs are already listed in term
order. The ONLY unknown is where the group boundaries fall, i.e. how the input
list partitions into consecutive AND terms.

WHAT IS ALREADY SOLVED (no help needed on these)
- AN12: PROVEN. 4 terms x 3 inputs. It is the logic-op (LOP) selector in BITBLT.
    O = NOT( (O3.a.XD) + (O2.a.D) + (O1.b.XD) + (O0.b.D) )
- AN15: high confidence. 5 terms x 3 inputs, next-state logic for one bus-
    sequencer state bit. First two terms are all-true and all-false state
    decodes, which is what a state machine's next state looks like.
- AN1 (4 candidates) and AN6 (10 candidates): small, low risk.

WHAT IS STILL OPEN (the real ask)
- AN17: 17 inputs, feeds the D input of state flip-flop P1010 via a NO2 gate.
    It is the next-state term for a bus-sequencer state bit. 17 inputs do not
    divide into uniform width terms, so it does not follow the neat pattern the
    others do. After filtering impossible/degenerate partitions there are 127
    plausible candidates left. This is the one gate we cannot pin down.
- AN2: 4 candidates, differ only in halftone (HOP) behaviour.

THE STATE MACHINE AN15/AN17 LIVE IN
Three flip-flops form the bus sequencer, all clocked on the internal address
strobe (IAS): P1004 (gated by BUSY), P1010, P1012. That is 8 states. AN15 and
AN17 compute the next state. The sequencer must: step through the 68000 bus
cycle, insert wait states while DTACK is not yet asserted, terminate on BERR,
and respect the 64 vs 63 word non-hog bus-cycle limit.

FILES IN THIS ZIP
- blitter-4051.sil     Atari's full netlist (Silos format): INSTANCE CELLTYPE
                       then nets in pin order. 1356 instances.
- blitter-cell-pins.txt  Pin order and notes for all 65 cell types.
- an_gates.txt         Just the four AN instances with their nets.
- an_context.txt       The AN gates plus every instance sharing a net with them
                       (the 1-hop neighbourhood), so the surrounding logic that
                       constrains the grouping is visible.
- AN_GATES_README.txt  This file.

HOW TO READ A LINE
  (P1011  AN17  P1011-O  P1012-Q P1010-XQ P1004-Q ... )
   ^instance ^cell ^output   ^then the 17 input nets, in term order.
Nets ending -Q / -XQ are a flip-flop's true / complement outputs. Nets ending
-O are another gate's output. So AN17's inputs are mostly state-FF outputs plus
a few combinational signals (P1092-O, P1094-O, P1003-O, P1005-O).

WHAT WOULD SETTLE IT
Either the original pri150ww.lib AOI cell definitions (the primitive that AN17
maps to), or a best-guess reconstruction of the AOI primitives that we can then
test by simulation against known blitter bus behaviour.
