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# STE_GSTMCU -- Single unit symbol
#
DEF STE_GSTMCU U 0 50 Y Y 1 L N
ALIAS C300589-001
F0 "U" -1250 6550 50 H V L TNN
F1 "STE_GSTMCU" -1250 6450 50 H V L TNB
F2 "Package_QFP:PQFP-144_28x28mm_P0.65mm" -1250 6650 50 H I L TNB
F3 "https://info-coach.fr/atari/hardware/STE-HW.php#mcu" -1250 6750 50 H I L TNN
DRAW
S -1250 6350 1250 -6350 0 0 10 f
X FC2 38 -1550 6300 300 R 50 50 0 0 I 
X FC1 39 -1550 6200 300 R 50 50 0 0 I 
X FC0 40 -1550 6100 300 R 50 50 0 0 I 
X ~BINT~ 60 -1550 5900 300 R 50 50 0 0 I 
X ~EINT3~ 30 -1550 5700 300 R 50 50 0 0 I 
X ~EINT5~ 31 -1550 5600 300 R 50 50 0 0 I 
X ~EINT7~ 32 -1550 5500 300 R 50 50 0 0 I 
X TEST 74 -1550 5300 300 R 50 50 0 0 I 
X CLK16 2 -1550 5100 300 R 50 50 0 0 I C
X CLK8 3 1550 5100 300 L 50 50 0 0 O C
X CLK0.5 6 1550 5000 300 L 50 50 0 0 O C
X CLK4 4 1550 4900 300 L 50 50 0 0 O C
X CLK2 5 1550 4800 300 L 50 50 0 0 O C
X ~RESET~ 66 -1550 4600 300 R 50 50 0 0 I 
X ~BERR~ 23 1550 4600 300 L 50 50 0 0 O 
X ~BGI~ 28 -1550 4400 300 R 50 50 0 0 I 
X ~BGACK~ 26 1550 4400 300 L 50 50 0 0 O 
X ~BGO~ 27 1550 4300 300 L 50 50 0 0 O 
X ~BR~ 29 1550 4200 300 L 50 50 0 0 T 
X ~AS~ 67 -1550 4000 300 R 50 50 0 0 I 
X ~UDS~ 68 -1550 3900 300 R 50 50 0 0 I 
X ~LDS~ 69 -1550 3800 300 R 50 50 0 0 I 
X R/~W~ 70 -1550 3700 300 R 50 50 0 0 I 
X ~DTACK~ 71 1550 4000 300 L 50 50 0 0 T 
X ~HDINT~ 15 -1550 3500 300 R 50 50 0 0 I 
X FDINT 16 -1550 3400 300 R 50 50 0 0 I 
X ~DISKINT~ 17 1550 3500 300 L 50 50 0 0 O 
X ~MFPINT~ 93 -1550 3200 300 R 50 50 0 0 I 
X ~IACK~ 83 1550 3200 300 L 50 50 0 0 O 
X ~MFPCS~ 92 1550 3100 300 L 50 50 0 0 O 
X SREQ 107 -1550 2900 300 R 50 50 0 0 I 
X ~SINT~ 105 1550 2900 300 L 50 50 0 0 O 
X ~SLOAD~ 106 1550 2800 300 L 50 50 0 0 O 
X ~RDY~ 135 -1550 2600 300 R 50 50 0 0 I 
X ~FCS~ 136 1550 2600 300 L 50 50 0 0 O 
X ~VMA~ 24 -1550 2400 300 R 50 50 0 0 I 
X ~VPA~ 25 1550 2400 300 L 50 50 0 0 O 
X 6850 48 1550 2300 300 L 50 50 0 0 O 
X ~PAD0X~ 94 -1550 2100 300 R 50 50 0 0 I 
X ~PAD0Y~ 95 -1550 2000 300 R 50 50 0 0 I 
X ~PAD1X~ 96 -1550 1900 300 R 50 50 0 0 I 
X ~PAD1Y~ 97 -1550 1800 300 R 50 50 0 0 I 
X ~PEN~ 137 -1550 1700 300 R 50 50 0 0 I 
X ~PADRST~ 98 1550 2100 300 L 50 50 0 0 O 
X ~JOYRH~ 99 1550 2000 300 L 50 50 0 0 O 
X ~JOYRL~ 100 1550 1900 300 L 50 50 0 0 O 
X ~JOYWE~ 101 1550 1800 300 L 50 50 0 0 O 
X JOYWL 102 1550 1700 300 L 50 50 0 0 O 
X ~BUTTON~ 103 1550 1600 300 L 50 50 0 0 O 
X ~DMA~ 132 1550 1400 300 L 50 50 0 0 O 
X ~RAM~ 133 1550 1300 300 L 50 50 0 0 O 
X ~DEV~ 134 1550 1200 300 L 50 50 0 0 O 
X ~IPL0~ 33 1550 1000 300 L 50 50 0 0 O 
X ~IPL1~ 34 1550 900 300 L 50 50 0 0 O 
X ~IPL2~ 35 1550 800 300 L 50 50 0 0 O 
X ~ROM0~ 7 1550 600 300 L 50 50 0 0 O 
X ~ROM1~ 8 1550 500 300 L 50 50 0 0 O 
X ~ROM2~ 9 1550 400 300 L 50 50 0 0 O 
X ~ROM3~ 10 1550 300 300 L 50 50 0 0 O 
X ~ROM4~ 11 1550 200 300 L 50 50 0 0 O 
X ~ROM5~ 12 1550 100 300 L 50 50 0 0 O 
X ~ROM6~ 13 1550 0 300 L 50 50 0 0 O 
X ~WE~ 121 1550 -200 300 L 50 50 0 0 O 
X ~CAS1L~ 122 1550 -300 300 L 50 50 0 0 O 
X ~CAS1H~ 123 1550 -400 300 L 50 50 0 0 O 
X ~RAS1~ 124 1550 -500 300 L 50 50 0 0 O 
X ~CAS0L~ 125 1550 -600 300 L 50 50 0 0 O 
X ~CAS0H~ 126 1550 -700 300 L 50 50 0 0 O 
X ~RAS0~ 127 1550 -800 300 L 50 50 0 0 O 
X MAD9 119 1550 -1000 300 L 50 50 0 0 O 
X MAD8 118 1550 -1100 300 L 50 50 0 0 O 
X MAD7 117 1550 -1200 300 L 50 50 0 0 O 
X MAD6 116 1550 -1300 300 L 50 50 0 0 O 
X MAD5 115 1550 -1400 300 L 50 50 0 0 O 
X MAD4 114 1550 -1500 300 L 50 50 0 0 O 
X MAD3 113 1550 -1600 300 L 50 50 0 0 O 
X MAD2 112 1550 -1700 300 L 50 50 0 0 O 
X MAD1 111 1550 -1800 300 L 50 50 0 0 O 
X MAD0 110 1550 -1900 300 L 50 50 0 0 O 
X ~WDAT~ 129 1550 -2100 300 L 50 50 0 0 O 
X ~RDAT~ 130 1550 -2200 300 L 50 50 0 0 O 
X LATCH 131 1550 -2300 300 L 50 50 0 0 O 
X ~DCYC~ 138 1550 -2500 300 L 50 50 0 0 O 
X ~CMPCS~ 139 1550 -2600 300 L 50 50 0 0 O 
X ~BLANK~ 140 1550 -2700 300 L 50 50 0 0 O 
X DE 141 1550 -2800 300 L 50 50 0 0 O 
X ~VSYNC~ 142 1550 -2900 300 L 50 50 0 0 O 
X ~HSYNC~ 143 1550 -3000 300 L 50 50 0 0 O 
X SNDIR 18 1550 -3200 300 L 50 50 0 0 O 
X SNDCS 19 1550 -3300 300 L 50 50 0 0 O 
X ~RTCWR~ 20 1550 -3500 300 L 50 50 0 0 O 
X ~RTCRD~ 21 1550 -3600 300 L 50 50 0 0 O 
X ~RTCCS~ 22 1550 -3700 300 L 50 50 0 0 O 
X A23 41 -1550 -3900 300 R 50 50 0 0 B 
X A22 42 -1550 -4000 300 R 50 50 0 0 B 
X A21 43 -1550 -4100 300 R 50 50 0 0 B 
X A20 44 -1550 -4200 300 R 50 50 0 0 B 
X A19 45 -1550 -4300 300 R 50 50 0 0 B 
X A18 46 -1550 -4400 300 R 50 50 0 0 B 
X A17 47 -1550 -4500 300 R 50 50 0 0 B 
X A16 49 -1550 -4600 300 R 50 50 0 0 B 
X A15 50 -1550 -4700 300 R 50 50 0 0 B 
X A14 51 -1550 -4800 300 R 50 50 0 0 B 
X A13 52 -1550 -4900 300 R 50 50 0 0 B 
X A12 53 -1550 -5000 300 R 50 50 0 0 B 
X A11 54 -1550 -5100 300 R 50 50 0 0 B 
X A10 55 -1550 -5200 300 R 50 50 0 0 B 
X A9 56 -1550 -5300 300 R 50 50 0 0 B 
X A8 57 -1550 -5400 300 R 50 50 0 0 B 
X A7 58 -1550 -5500 300 R 50 50 0 0 B 
X A6 59 -1550 -5600 300 R 50 50 0 0 B 
X A5 61 -1550 -5700 300 R 50 50 0 0 B 
X A4 62 -1550 -5800 300 R 50 50 0 0 B 
X A3 63 -1550 -5900 300 R 50 50 0 0 B 
X A2 64 -1550 -6000 300 R 50 50 0 0 B 
X A1 65 -1550 -6100 300 R 50 50 0 0 B 
X D15 75 1550 -3900 300 L 50 50 0 0 B 
X D14 76 1550 -4000 300 L 50 50 0 0 B 
X D13 77 1550 -4100 300 L 50 50 0 0 B 
X D12 78 1550 -4200 300 L 50 50 0 0 B 
X D11 79 1550 -4300 300 L 50 50 0 0 B 
X D10 80 1550 -4400 300 L 50 50 0 0 B 
X D9 81 1550 -4500 300 L 50 50 0 0 B 
X D8 82 1550 -4600 300 L 50 50 0 0 B 
X D7 84 1550 -4700 300 L 50 50 0 0 B 
X D6 85 1550 -4800 300 L 50 50 0 0 B 
X D5 86 1550 -4900 300 L 50 50 0 0 B 
X D4 87 1550 -5000 300 L 50 50 0 0 B 
X D3 88 1550 -5100 300 L 50 50 0 0 B 
X D2 89 1550 -5200 300 L 50 50 0 0 B 
X D1 90 1550 -5300 300 L 50 50 0 0 B 
X D0 91 1550 -5400 300 L 50 50 0 0 B 
X VCC 36 -600 6650 300 D 50 50 0 0 W 
X VCC 72 -300 6650 300 D 50 50 0 0 W 
X VCC 108 0 6650 300 D 50 50 0 0 W 
X VCC 120 300 6650 300 D 50 50 0 0 W 
X VCC 144 600 6650 300 D 50 50 0 0 W 
X GND 1 -600 -6650 300 U 50 50 0 0 W 
X GND 37 -300 -6650 300 U 50 50 0 0 W 
X GND 73 0 -6650 300 U 50 50 0 0 W 
X GND 109 300 -6650 300 U 50 50 0 0 W 
X GND 128 600 -6650 300 U 50 50 0 0 W 
ENDDRAW
ENDDEF
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# STE_GSTMCU -- Multiple units symbol
#
DEF STE_GSTMCU_MU U 0 50 Y Y 26 L N
ALIAS C300589-001_mu
F0 "U" -500 300 50 H V L TNN
F1 "STE_GSTMCU_mu_mu" -500 200 50 H V L TNB
F2 "Package_QFP:PQFP-144_28x28mm_P0.65mm" -500 400 50 H I L TNN
F3 "https://info-coach.fr/atari/hardware/STE-HW.php#mcu" -500 500 50 H I L TNN
DRAW
#
# --- --- --- ---
# Clocking system
#
T 0 -500 100 50 1 1 0 "Clocking system" Normal 0 L T
S -350 0 350 -500 1 0 10 f
X CLK16 2 -650 -100 300 R 50 50 1 0 I C
X CLK8 3 650 -100 300 L 50 50 1 0 O C
X CLK0.5 6 650 -200 300 L 50 50 1 0 O C
X CLK4 4 650 -300 300 L 50 50 1 0 O C
X CLK2 5 650 -400 300 L 50 50 1 0 O C
#
# --- --- --- ---
# System control signals
#
T 0 -500 100 50 1 2 0 "System control signals" Normal 0 L T
S -400 0 400 -200 2 0 10 f
X ~RESET~ 66 -700 -100 300 R 50 50 2 0 I 
X ~BERR~ 23 700 -100 300 L 50 50 2 0 O 
#
# --- --- --- ---
# Bus arbitration control
#
T 0 -500 100 50 1 3 0 "Bus arbitration control" Normal 0 L T
S -350 0 350 -400 3 0 10 f
X ~BGI~ 28 -650 -100 300 R 50 50 3 0 I 
X ~BGACK~ 26 650 -100 300 L 50 50 3 0 O 
X ~BGO~ 27 650 -200 300 L 50 50 3 0 O 
X ~BR~ 29 650 -300 300 L 50 50 3 0 T 
#
# --- --- --- ---
# Asynchronous bus control
#
T 0 -500 100 50 1 4 0 "Asynchronous bus control" Normal 0 L T
S -350 0 350 -500 4 0 10 f
X ~AS~ 67 -650 -100 300 R 50 50 4 0 I 
X ~UDS~ 68 -650 -200 300 R 50 50 4 0 I 
X ~LDS~ 69 -650 -300 300 R 50 50 4 0 I 
X R/~W~ 70 -650 -400 300 R 50 50 4 0 I 
X ~DTACK~ 71 650 -100 300 L 50 50 4 0 T 
#
# --- --- --- ---
# GLUE to MMU signals
#
T 0 -500 100 50 1 5 0 "GLUE to MMU signals" Normal 0 L T
S -200 0 200 -400 5 0 10 f
X ~DMA~ 132 500 -100 300 L 50 50 5 0 O 
X ~RAM~ 133 500 -200 300 L 50 50 5 0 O 
X ~DEV~ 134 500 -300 300 L 50 50 5 0 O 
#
# --- --- --- ---
# Drives interrupt signals
#
T 0 -500 100 50 1 6 0 "Drives interrupt signals" Normal 0 L T
S -450 0 450 -300 6 0 10 f
X ~HDINT~ 15 -750 -100 300 R 50 50 6 0 I 
X FDINT 16 -750 -200 300 R 50 50 6 0 I 
X ~DISKINT~ 17 750 -100 300 L 50 50 6 0 O 
#
# --- --- --- ---
# MFP Interruption control
#
T 0 -500 100 50 1 7 0 "MFP Interruption control" Normal 0 L T
S -450 0 450 -300 7 0 10 f
X ~MFPINT~ 93 -750 -100 300 R 50 50 7 0 I 
X ~IACK~ 83 750 -100 300 L 50 50 7 0 O 
X ~MFPCS~ 92 750 -200 300 L 50 50 7 0 O 
#
# --- --- --- ---
# Interrupt Priority Level selection
#
T 0 -500 100 50 1 8 0 "Interrupt Priority Level selection" Normal 0 L T
S -200 0 200 -400 8 0 10 f
X ~IPL0~ 33 500 -100 300 L 50 50 8 0 O 
X ~IPL1~ 34 500 -200 300 L 50 50 8 0 O 
X ~IPL2~ 35 500 -300 300 L 50 50 8 0 O 
#
# --- --- --- ---
# Function Code
#
T 0 -500 100 50 1 9 0 "Function Code" Normal 0 L T
S -150 0 150 -400 9 0 10 f
X FC2 38 -450 -100 300 R 50 50 9 0 I 
X FC1 39 -450 -200 300 R 50 50 9 0 I 
X FC0 40 -450 -300 300 R 50 50 9 0 I 
#
# --- --- --- ---
# ROM area selection
#
T 0 -500 100 50 1 10 0 "ROM area selection" Normal 0 L T
S -200 0 200 -800 10 0 10 f
X ~ROM0~ 7 500 -100 300 L 50 50 10 0 O 
X ~ROM1~ 8 500 -200 300 L 50 50 10 0 O 
X ~ROM2~ 9 500 -300 300 L 50 50 10 0 O 
X ~ROM3~ 10 500 -400 300 L 50 50 10 0 O 
X ~ROM4~ 11 500 -500 300 L 50 50 10 0 O 
X ~ROM5~ 12 500 -600 300 L 50 50 10 0 O 
X ~ROM6~ 13 500 -700 300 L 50 50 10 0 O 
#
# --- --- --- ---
# RAM access control
#
T 0 -500 100 50 1 11 0 "RAM access control" Normal 0 L T
S -250 0 250 -800 11 0 10 f
X ~WE~ 121 550 -100 300 L 50 50 11 0 O 
X ~CAS1L~ 122 550 -200 300 L 50 50 11 0 O 
X ~CAS1H~ 123 550 -300 300 L 50 50 11 0 O 
X ~RAS1~ 124 550 -400 300 L 50 50 11 0 O 
X ~CAS0L~ 125 550 -500 300 L 50 50 11 0 O 
X ~CAS0H~ 126 550 -600 300 L 50 50 11 0 O 
X ~RAS0~ 127 550 -700 300 L 50 50 11 0 O 
#
# --- --- --- ---
# Multiplexed ADDress bus (RAM)
#
T 0 -500 100 50 1 12 0 "Multiplexed ADDress bus (RAM)" Normal 0 L T
S -150 0 150 -1100 12 0 10 f
X MAD9 119 450 -100 300 L 50 50 12 0 O 
X MAD8 118 450 -200 300 L 50 50 12 0 O 
X MAD7 117 450 -300 300 L 50 50 12 0 O 
X MAD6 116 450 -400 300 L 50 50 12 0 O 
X MAD5 115 450 -500 300 L 50 50 12 0 O 
X MAD4 114 450 -600 300 L 50 50 12 0 O 
X MAD3 113 450 -700 300 L 50 50 12 0 O 
X MAD2 112 450 -800 300 L 50 50 12 0 O 
X MAD1 111 450 -900 300 L 50 50 12 0 O 
X MAD0 110 450 -1000 300 L 50 50 12 0 O 
#
# --- --- --- ---
# RAM access control for the Shifter
#
T 0 -500 100 50 1 13 0 "RAM access control for the Shifter" Normal 0 L T
S -200 0 200 -400 13 0 10 f
X ~WDAT~ 129 500 -100 300 L 50 50 13 0 O 
X ~RDAT~ 130 500 -200 300 L 50 50 13 0 O 
X LATCH 131 500 -300 300 L 50 50 13 0 O 
#
# --- --- --- ---
# Video synchronisation
#
T 0 -500 100 50 1 14 0 "Video synchronisation" Normal 0 L T
S -250 0 250 -700 14 0 10 f
X ~DCYC~ 138 550 -100 300 L 50 50 14 0 O 
X ~CMPCS~ 139 550 -200 300 L 50 50 14 0 O 
X ~BLANK~ 140 550 -300 300 L 50 50 14 0 O 
X DE 141 550 -400 300 L 50 50 14 0 O 
X ~VSYNC~ 142 550 -500 300 L 50 50 14 0 O 
X ~HSYNC~ 143 550 -600 300 L 50 50 14 0 O 
#
# --- --- --- ---
# DMA Sound control
#
T 0 -500 100 50 1 15 0 "DMA Sound control" Normal 0 L T
S -350 0 350 -300 15 0 10 f
X SREQ 107 -650 -100 300 R 50 50 15 0 I 
X ~SINT~ 105 650 -100 300 L 50 50 15 0 O 
X ~SLOAD~ 106 650 -200 300 L 50 50 15 0 O 
#
# --- --- --- ---
# Blitter control
#
T 0 -500 100 50 1 16 0 "Blitter control" Normal 0 L T
S -200 0 200 -200 16 0 10 f
X ~BINT~ 60 -500 -100 300 R 50 50 16 0 I 
#
# --- --- --- ---
# DMA chip control
#
T 0 -500 100 50 1 17 0 "DMA chip control" Normal 0 L T
S -300 0 300 -200 17 0 10 f
X ~RDY~ 135 -600 -100 300 R 50 50 17 0 I 
X ~FCS~ 136 600 -100 300 L 50 50 17 0 O 
#
# --- --- --- ---
# MC6800 Peripheral control
#
T 0 -500 100 50 1 18 0 "MC6800 Peripheral control" Normal 0 L T
S -300 0 300 -300 18 0 10 f
X ~VMA~ 24 -600 -100 300 R 50 50 18 0 I 
X ~VPA~ 25 600 -100 300 L 50 50 18 0 O 
X 6850 48 600 -200 300 L 50 50 18 0 O 
#
# --- --- --- ---
# Programmable Sound Generator control
#
T 0 -500 100 50 1 19 0 "Programmable Sound Generator control" Normal 0 L T
S -200 0 200 -300 19 0 10 f
X SNDIR 18 500 -100 300 L 50 50 19 0 O 
X SNDCS 19 500 -200 300 L 50 50 19 0 O 
#
# --- --- --- ---
# Real Time Clock control
#
T 0 -500 100 50 1 20 0 "Real Time Clock control" Normal 0 L T
S -250 0 250 -400 20 0 10 f
X ~RTCWR~ 20 550 -100 300 L 50 50 20 0 O 
X ~RTCRD~ 21 550 -200 300 L 50 50 20 0 O 
X ~RTCCS~ 22 550 -300 300 L 50 50 20 0 O 
#
# --- --- --- ---
# Extended joysticks and paddles ports
#
T 0 -500 100 50 1 21 0 "Extended joysticks and paddles ports" Normal 0 L T
S -450 0 450 -700 21 0 10 f
X ~PAD0X~ 94 -750 -100 300 R 50 50 21 0 I 
X ~PAD0Y~ 95 -750 -200 300 R 50 50 21 0 I 
X ~PAD1X~ 96 -750 -300 300 R 50 50 21 0 I 
X ~PAD1Y~ 97 -750 -400 300 R 50 50 21 0 I 
X ~PEN~ 137 -750 -500 300 R 50 50 21 0 I 
X ~PADRST~ 98 750 -100 300 L 50 50 21 0 O 
X ~JOYRH~ 99 750 -200 300 L 50 50 21 0 O 
X ~JOYRL~ 100 750 -300 300 L 50 50 21 0 O 
X ~JOYWE~ 101 750 -400 300 L 50 50 21 0 O 
X JOYWL 102 750 -500 300 L 50 50 21 0 O 
X ~BUTTON~ 103 750 -600 300 L 50 50 21 0 O 
#
# --- --- --- ---
# External interrupt
#
T 0 -500 100 50 1 22 0 "External interrupt" Normal 0 L T
S -250 0 250 -400 22 0 10 f
X ~EINT3~ 30 -550 -100 300 R 50 50 22 0 I 
X ~EINT5~ 31 -550 -200 300 R 50 50 22 0 I 
X ~EINT7~ 32 -550 -300 300 R 50 50 22 0 I 
#
# --- --- --- ---
# Test
#
T 0 -500 100 50 1 23 0 "Test" Normal 0 L T
S -150 0 150 -200 23 0 10 f
X TEST 74 -450 -100 300 R 50 50 23 0 I 
#
# --- --- --- ---
# CPU bus address
#
T 0 -500 100 50 1 24 0 "CPU bus address" Normal 0 L T
S -150 0 150 -2400 24 0 10 f
X A23 41 450 -100 300 L 50 50 24 0 B 
X A22 42 450 -200 300 L 50 50 24 0 B 
X A21 43 450 -300 300 L 50 50 24 0 B 
X A20 44 450 -400 300 L 50 50 24 0 B 
X A19 45 450 -500 300 L 50 50 24 0 B 
X A18 46 450 -600 300 L 50 50 24 0 B 
X A17 47 450 -700 300 L 50 50 24 0 B 
X A16 49 450 -800 300 L 50 50 24 0 B 
X A15 50 450 -900 300 L 50 50 24 0 B 
X A14 51 450 -1000 300 L 50 50 24 0 B 
X A13 52 450 -1100 300 L 50 50 24 0 B 
X A12 53 450 -1200 300 L 50 50 24 0 B 
X A11 54 450 -1300 300 L 50 50 24 0 B 
X A10 55 450 -1400 300 L 50 50 24 0 B 
X A9 56 450 -1500 300 L 50 50 24 0 B 
X A8 57 450 -1600 300 L 50 50 24 0 B 
X A7 58 450 -1700 300 L 50 50 24 0 B 
X A6 59 450 -1800 300 L 50 50 24 0 B 
X A5 61 450 -1900 300 L 50 50 24 0 B 
X A4 62 450 -2000 300 L 50 50 24 0 B 
X A3 63 450 -2100 300 L 50 50 24 0 B 
X A2 64 450 -2200 300 L 50 50 24 0 B 
X A1 65 450 -2300 300 L 50 50 24 0 B 
#
# --- --- --- ---
# CPU bus data
#
T 0 -500 100 50 1 25 0 "CPU bus data" Normal 0 L T
S -150 0 150 -1700 25 0 10 f
X D15 75 450 -100 300 L 50 50 25 0 B 
X D14 76 450 -200 300 L 50 50 25 0 B 
X D13 77 450 -300 300 L 50 50 25 0 B 
X D12 78 450 -400 300 L 50 50 25 0 B 
X D11 79 450 -500 300 L 50 50 25 0 B 
X D10 80 450 -600 300 L 50 50 25 0 B 
X D9 81 450 -700 300 L 50 50 25 0 B 
X D8 82 450 -800 300 L 50 50 25 0 B 
X D7 84 450 -900 300 L 50 50 25 0 B 
X D6 85 450 -1000 300 L 50 50 25 0 B 
X D5 86 450 -1100 300 L 50 50 25 0 B 
X D4 87 450 -1200 300 L 50 50 25 0 B 
X D3 88 450 -1300 300 L 50 50 25 0 B 
X D2 89 450 -1400 300 L 50 50 25 0 B 
X D1 90 450 -1500 300 L 50 50 25 0 B 
X D0 91 450 -1600 300 L 50 50 25 0 B 
#
# --- --- --- ---
# Power supply
#
T 0 -500 100 50 1 26 0 "Power supply" Normal 0 L T
S -800 0 800 -1400 26 0 10 f
X VCC 36 -1100 -100 300 R 50 50 26 0 W 
X VCC 72 -1100 -400 300 R 50 50 26 0 W 
X VCC 108 -1100 -700 300 R 50 50 26 0 W 
X VCC 120 -1100 -1000 300 R 50 50 26 0 W 
X VCC 144 -1100 -1300 300 R 50 50 26 0 W 
X GND 1 -500 -1700 300 U 50 50 26 0 W 
X GND 37 -200 -1700 300 U 50 50 26 0 W 
X GND 73 100 -1700 300 U 50 50 26 0 W 
X GND 109 400 -1700 300 U 50 50 26 0 W 
X GND 128 700 -1700 300 U 50 50 26 0 W 
ENDDRAW
ENDDEF
