Timing Report

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Design Name main_top
Device, Speed (SpeedFile Version) XC95288XL, -10 (3.0)
Date Created Mon Mar 17 19:34:16 2025
Created By Timing Report Generator: version P.20131013
Copyright Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for CLKCPU_OBUF.Q
Clock to Setup (tCYC) 11.000 ns.
Pad to Pad Delay (tPD) 18.700 ns.
Setup to Clock at the Pad (tSU) 8.300 ns.
Clock Pad to Output Pad Delay (tCO) 30.100 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
AUTO_TS_F2F 0.0 11.8 453 453
AUTO_TS_P2P 0.0 30.1 184 184
AUTO_TS_P2F 0.0 10.1 205 205
AUTO_TS_F2P 0.0 20.4 77 77


Constraint: TS1000

Description: PERIOD:PERIOD_BUSEN_IRQ.CLKF:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_CLKCPU_OBUF.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_CLK7M_RAW:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_CLK7M.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_CLK100M:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
BGACK_INT.Q to SPEED_D.D 0.000 11.800 -11.800
M6800BUS/Q<0>.Q to VMA.D 0.000 11.000 -11.000
M6800BUS/Q<1>.Q to VMA.D 0.000 11.000 -11.000
M6800BUS/Q<2>.Q to VMA.D 0.000 11.000 -11.000
M6800BUS/Q<3>.Q to VMA.D 0.000 11.000 -11.000
SDRAM/BCOUNT<0>.Q to SDRAM/address<10>.D 0.000 11.000 -11.000
SDRAM/BCOUNT<1>.Q to SDRAM/address<10>.D 0.000 11.000 -11.000
SDRAM/BCOUNT<1>.Q to SDRAM/cycle<2>.D 0.000 11.000 -11.000
SDRAM/BURSTING.Q to SDRAM/address<10>.D 0.000 11.000 -11.000
SDRAM/BURSTING.Q to SDRAM/address<1>.D 0.000 11.000 -11.000
SDRAM/BURSTING.Q to SDRAM/cycle<2>.D 0.000 11.000 -11.000
SDRAM/address<0>.Q to SDRAM/address<0>.D 0.000 11.000 -11.000
SDRAM/address<10>.Q to SDRAM/address<10>.D 0.000 11.000 -11.000
SDRAM/address<1>.Q to SDRAM/address<1>.D 0.000 11.000 -11.000
SDRAM/can_start.Q to SDRAM/address<0>.D 0.000 11.000 -11.000
SDRAM/can_start.Q to SDRAM/address<10>.D 0.000 11.000 -11.000
SDRAM/can_start.Q to SDRAM/address<1>.D 0.000 11.000 -11.000
SDRAM/cycle<0>.Q to SDRAM/address<0>.D 0.000 11.000 -11.000
SDRAM/cycle<0>.Q to SDRAM/address<10>.D 0.000 11.000 -11.000
SDRAM/cycle<0>.Q to SDRAM/address<1>.D 0.000 11.000 -11.000
SDRAM/cycle<0>.Q to SDRAM/cycle<0>.D 0.000 11.000 -11.000
SDRAM/cycle<0>.Q to SDRAM/cycle<2>.D 0.000 11.000 -11.000
SDRAM/cycle<1>.Q to SDRAM/address<0>.D 0.000 11.000 -11.000
SDRAM/cycle<1>.Q to SDRAM/address<10>.D 0.000 11.000 -11.000
SDRAM/cycle<1>.Q to SDRAM/address<1>.D 0.000 11.000 -11.000
SDRAM/cycle<1>.Q to SDRAM/cycle<0>.D 0.000 11.000 -11.000
SDRAM/cycle<1>.Q to SDRAM/cycle<2>.D 0.000 11.000 -11.000
SDRAM/cycle<2>.Q to SDRAM/address<0>.D 0.000 11.000 -11.000
SDRAM/cycle<2>.Q to SDRAM/address<10>.D 0.000 11.000 -11.000
SDRAM/cycle<2>.Q to SDRAM/address<1>.D 0.000 11.000 -11.000
SDRAM/cycle<2>.Q to SDRAM/cycle<0>.D 0.000 11.000 -11.000
SDRAM/cycle<3>.Q to SDRAM/address<0>.D 0.000 11.000 -11.000
SDRAM/cycle<3>.Q to SDRAM/address<10>.D 0.000 11.000 -11.000
SDRAM/cycle<3>.Q to SDRAM/address<1>.D 0.000 11.000 -11.000
SDRAM/cycle<3>.Q to SDRAM/cycle<0>.D 0.000 11.000 -11.000
SDRAM/cycle_type.Q to SDRAM/address<10>.D 0.000 11.000 -11.000
SDRAM/cycle_type.Q to SDRAM/address<1>.D 0.000 11.000 -11.000
SDRAM/ready.Q to SDRAM/address<0>.D 0.000 11.000 -11.000
SDRAM/ready.Q to SDRAM/address<10>.D 0.000 11.000 -11.000
SDRAM/ready.Q to SDRAM/address<1>.D 0.000 11.000 -11.000
SDRAM/refresh_req.Q to SDRAM/cycle<0>.D 0.000 11.000 -11.000
VMA.Q to VMA.D 0.000 11.000 -11.000
AS_RESYNC<0>.Q to AS.D 0.000 10.000 -10.000
AS_RESYNC<0>.Q to AS_RESYNC<1>.D 0.000 10.000 -10.000
AS_RESYNC<0>.Q to BG.D 0.000 10.000 -10.000
AS_RESYNC<0>.Q to DTACK_D.D 0.000 10.000 -10.000
AS_RESYNC<0>.Q to LDS.D 0.000 10.000 -10.000
AS_RESYNC<0>.Q to UDS.D 0.000 10.000 -10.000
AS_RESYNC<1>.Q to DTACK_D.D 0.000 10.000 -10.000
AS_RESYNC<1>.Q to LDS.D 0.000 10.000 -10.000
AS_RESYNC<1>.Q to UDS.D 0.000 10.000 -10.000
ATA/ASDLY.Q to ATA/ASDLY2.D 0.000 10.000 -10.000
ATA/ASDLY.Q to IOR.D 0.000 10.000 -10.000
ATA/ASDLY2.Q to DTACK_IDE.D 0.000 10.000 -10.000
ATA/ASDLY2.Q to IOW.D 0.000 10.000 -10.000
BGACK_INT.Q to HIGHZ.D 0.000 10.000 -10.000
CLK7M.Q to CLKCPU.D 0.000 10.000 -10.000
CLKCPU.Q to CLKCPU.D 0.000 10.000 -10.000
CLOCKS/CLK7M_D<0>.Q to CLOCKS/CLK7M_D<0>.D 0.000 10.000 -10.000
CLOCKS/CLK7M_D<0>.Q to CLOCKS/CLK7M_D<1>.D 0.000 10.000 -10.000
CLOCKS/CLK7M_D<1>.Q to CLOCKS/CLK7M_D<0>.D 0.000 10.000 -10.000
CLOCKS/CLK7M_D<1>.Q to CLOCKS/CLK7M_D<2>.D 0.000 10.000 -10.000
CLOCKS/CLK7M_D<2>.Q to CLOCKS/CLK7M_D<0>.D 0.000 10.000 -10.000
CLOCKS/CLK7M_D<2>.Q to CLOCKS/CLK7M_D<3>.D 0.000 10.000 -10.000
CLOCKS/CLK7M_D<3>.Q to CLK7M.D 0.000 10.000 -10.000
CLOCKS/SPEED_D.Q to CLKCPU.D 0.000 10.000 -10.000
DSACK1_SYNC.Q to DSACK1_SYNC.D 0.000 10.000 -10.000
DTACK_RESYNC<0>.Q to DTACK_D.D 0.000 10.000 -10.000
E.Q to E.D 0.000 10.000 -10.000
M6800BUS/Q<0>.Q to DSACK1_SYNC.D 0.000 10.000 -10.000
M6800BUS/Q<0>.Q to E.D 0.000 10.000 -10.000
M6800BUS/Q<0>.Q to M6800BUS/Q<1>.D 0.000 10.000 -10.000
M6800BUS/Q<0>.Q to M6800BUS/Q<2>.D 0.000 10.000 -10.000
M6800BUS/Q<0>.Q to M6800BUS/Q<3>.D 0.000 10.000 -10.000
M6800BUS/Q<1>.Q to DSACK1_SYNC.D 0.000 10.000 -10.000
M6800BUS/Q<1>.Q to E.D 0.000 10.000 -10.000
M6800BUS/Q<1>.Q to M6800BUS/Q<1>.D 0.000 10.000 -10.000
M6800BUS/Q<1>.Q to M6800BUS/Q<2>.D 0.000 10.000 -10.000
M6800BUS/Q<1>.Q to M6800BUS/Q<3>.D 0.000 10.000 -10.000
M6800BUS/Q<2>.Q to DSACK1_SYNC.D 0.000 10.000 -10.000
M6800BUS/Q<2>.Q to E.D 0.000 10.000 -10.000
M6800BUS/Q<2>.Q to M6800BUS/Q<1>.D 0.000 10.000 -10.000
M6800BUS/Q<2>.Q to M6800BUS/Q<3>.D 0.000 10.000 -10.000
M6800BUS/Q<3>.Q to DSACK1_SYNC.D 0.000 10.000 -10.000
M6800BUS/Q<3>.Q to E.D 0.000 10.000 -10.000
M6800BUS/Q<3>.Q to M6800BUS/Q<1>.D 0.000 10.000 -10.000
M6800BUS/Q<3>.Q to M6800BUS/Q<3>.D 0.000 10.000 -10.000
RAMOE.Q to SDRAM/BURSTING.D 0.000 10.000 -10.000
RAMOE.Q to SDRAM/bank<0>.CE 0.000 10.000 -10.000
RAMOE.Q to SDRAM/bank<1>.CE 0.000 10.000 -10.000
RAMOE.Q to SDRAM/can_start.D 0.000 10.000 -10.000
RAMOE.Q to SDRAM/command<2>.D 0.000 10.000 -10.000
RAMOE.Q to SDRAM/cycle<0>.D 0.000 10.000 -10.000
RAMOE.Q to SDRAM/cycle_type.D 0.000 10.000 -10.000
SDRAM/BCOUNT<0>.Q to SDRAM/BCOUNT<0>.D 0.000 10.000 -10.000
SDRAM/BCOUNT<0>.Q to SDRAM/BCOUNT<1>.D 0.000 10.000 -10.000
SDRAM/BCOUNT<0>.Q to SDRAM/address<0>.D 0.000 10.000 -10.000
SDRAM/BCOUNT<0>.Q to SDRAM/cycle<2>.D 0.000 10.000 -10.000
SDRAM/BCOUNT<1>.Q to SDRAM/BCOUNT<1>.D 0.000 10.000 -10.000
SDRAM/BCOUNT<1>.Q to SDRAM/address<1>.D 0.000 10.000 -10.000
SDRAM/BURSTING.Q to SDRAM/address<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<11>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<3>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<4>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<5>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<6>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<7>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<8>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/INIT/COUNTER<9>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<0>.Q to SDRAM/ready.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<10>.Q to SDRAM/INIT/COUNTER<11>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<10>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<10>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<10>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<10>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<10>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<10>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<10>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<10>.Q to SDRAM/refresh.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<11>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<11>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<11>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<11>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<11>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<11>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<11>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<11>.Q to SDRAM/ready.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<12>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<12>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<12>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<12>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<12>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<12>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<12>.Q to SDRAM/ready.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<13>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<13>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<13>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<13>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<13>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<13>.Q to SDRAM/ready.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<11>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<3>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<4>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<5>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<6>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<7>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<8>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/INIT/COUNTER<9>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<1>.Q to SDRAM/ready.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/INIT/COUNTER<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/INIT/COUNTER<11>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/INIT/COUNTER<3>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/INIT/COUNTER<4>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/INIT/COUNTER<5>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/INIT/COUNTER<6>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/INIT/COUNTER<7>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/INIT/COUNTER<8>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/INIT/COUNTER<9>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<2>.Q to SDRAM/ready.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/INIT/COUNTER<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/INIT/COUNTER<11>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/INIT/COUNTER<4>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/INIT/COUNTER<5>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/INIT/COUNTER<6>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/INIT/COUNTER<7>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/INIT/COUNTER<8>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/INIT/COUNTER<9>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<3>.Q to SDRAM/ready.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/INIT/COUNTER<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/INIT/COUNTER<11>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/INIT/COUNTER<5>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/INIT/COUNTER<6>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/INIT/COUNTER<7>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/INIT/COUNTER<8>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/INIT/COUNTER<9>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<4>.Q to SDRAM/ready.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/INIT/COUNTER<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/INIT/COUNTER<11>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/INIT/COUNTER<6>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/INIT/COUNTER<7>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/INIT/COUNTER<8>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/INIT/COUNTER<9>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<5>.Q to SDRAM/ready.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/INIT/COUNTER<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/INIT/COUNTER<11>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/INIT/COUNTER<7>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/INIT/COUNTER<8>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/INIT/COUNTER<9>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<6>.Q to SDRAM/ready.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/INIT/COUNTER<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/INIT/COUNTER<11>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/INIT/COUNTER<8>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/INIT/COUNTER<9>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<7>.Q to SDRAM/ready.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<8>.Q to SDRAM/INIT/COUNTER<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<8>.Q to SDRAM/INIT/COUNTER<11>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<8>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<8>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<8>.Q to SDRAM/INIT/COUNTER<9>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<8>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<8>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<8>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<9>.Q to SDRAM/INIT/COUNTER<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<9>.Q to SDRAM/INIT/COUNTER<11>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<9>.Q to SDRAM/INIT/COUNTER<12>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<9>.Q to SDRAM/INIT/COUNTER<13>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<9>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<9>.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<9>.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<9>.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/INIT/COUNTER<9>.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/WAIT_BLOCK.Q to SDRAM/WAIT_BLOCK.D 0.000 10.000 -10.000
SDRAM/WAIT_BLOCK.Q to STERM.D 0.000 10.000 -10.000
SDRAM/address<11>.Q to SDRAM/address<11>.D 0.000 10.000 -10.000
SDRAM/address<12>.Q to SDRAM/address<12>.D 0.000 10.000 -10.000
SDRAM/address<2>.Q to SDRAM/address<2>.D 0.000 10.000 -10.000
SDRAM/address<3>.Q to SDRAM/address<3>.D 0.000 10.000 -10.000
SDRAM/address<4>.Q to SDRAM/address<4>.D 0.000 10.000 -10.000
SDRAM/address<5>.Q to SDRAM/address<5>.D 0.000 10.000 -10.000
SDRAM/address<6>.Q to SDRAM/address<6>.D 0.000 10.000 -10.000
SDRAM/address<7>.Q to SDRAM/address<7>.D 0.000 10.000 -10.000
SDRAM/address<8>.Q to SDRAM/address<8>.D 0.000 10.000 -10.000
SDRAM/address<9>.Q to SDRAM/address<9>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/BURSTING.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/address<11>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/address<12>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/address<2>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/address<3>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/address<4>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/address<5>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/address<6>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/address<7>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/address<8>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/address<9>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/bank<0>.CE 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/bank<1>.CE 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/can_start.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/command<2>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/cycle<0>.D 0.000 10.000 -10.000
SDRAM/can_start.Q to SDRAM/cycle_type.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/BCOUNT<0>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/BCOUNT<1>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/BURSTING.CE 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/WAIT_BLOCK.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/address<11>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/address<12>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/address<2>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/address<3>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/address<4>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/address<5>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/address<6>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/address<7>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/address<8>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/address<9>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/bank<0>.CE 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/bank<1>.CE 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/can_start.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/command<0>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/command<1>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/command<2>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/cycle<1>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/cycle<3>.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/cycle_type.D 0.000 10.000 -10.000
SDRAM/cycle<0>.Q to SDRAM/refresh_req.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/BCOUNT<0>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/BCOUNT<1>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/BURSTING.CE 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/WAIT_BLOCK.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/address<11>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/address<12>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/address<2>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/address<3>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/address<4>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/address<5>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/address<6>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/address<7>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/address<8>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/address<9>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/bank<0>.CE 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/bank<1>.CE 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/can_start.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/command<0>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/command<1>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/command<2>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/cycle<3>.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/cycle_type.D 0.000 10.000 -10.000
SDRAM/cycle<1>.Q to SDRAM/refresh_req.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/BCOUNT<0>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/BCOUNT<1>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/BURSTING.CE 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/WAIT_BLOCK.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/address<11>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/address<12>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/address<2>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/address<3>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/address<4>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/address<5>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/address<6>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/address<7>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/address<8>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/address<9>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/bank<0>.CE 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/bank<1>.CE 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/can_start.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/command<0>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/command<1>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/command<2>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/cycle<2>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/cycle<3>.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/cycle_type.D 0.000 10.000 -10.000
SDRAM/cycle<2>.Q to SDRAM/refresh_req.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/BCOUNT<0>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/BCOUNT<1>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/BURSTING.CE 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/WAIT_BLOCK.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/address<11>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/address<12>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/address<2>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/address<3>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/address<4>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/address<5>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/address<6>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/address<7>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/address<8>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/address<9>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/bank<0>.CE 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/bank<1>.CE 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/can_start.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/command<0>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/command<1>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/command<2>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/cycle<2>.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/cycle_type.D 0.000 10.000 -10.000
SDRAM/cycle<3>.Q to SDRAM/refresh_req.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/BCOUNT<0>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/BCOUNT<1>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/WAIT_BLOCK.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/address<0>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/address<11>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/address<12>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/address<2>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/address<3>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/address<4>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/address<5>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/address<6>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/address<7>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/address<8>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/address<9>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/command<0>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/command<1>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/command<2>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/cycle<2>.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/cycle_type.D 0.000 10.000 -10.000
SDRAM/cycle_type.Q to SDRAM/refresh_req.D 0.000 10.000 -10.000
SDRAM/init_address<10>.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/BURSTING.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/address<11>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/address<12>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/address<2>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/address<3>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/address<4>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/address<5>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/address<6>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/address<7>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/address<8>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/address<9>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/bank<0>.CE 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/bank<1>.CE 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/can_start.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/command<2>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/cycle<0>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/cycle_type.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/init_address<10>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/init_address<5>.CE 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/init_command<0>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/init_command<1>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/init_command<2>.D 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/ready.CE 0.000 10.000 -10.000
SDRAM/ready.Q to SDRAM/refresh.D 0.000 10.000 -10.000
SDRAM/refresh.Q to SDRAM/refresh_d.D 0.000 10.000 -10.000
SDRAM/refresh.Q to SDRAM/refresh_req.D 0.000 10.000 -10.000
SDRAM/refresh_d.Q to SDRAM/refresh_req.D 0.000 10.000 -10.000
SDRAM/refresh_req.Q to SDRAM/BURSTING.D 0.000 10.000 -10.000
SDRAM/refresh_req.Q to SDRAM/bank<0>.CE 0.000 10.000 -10.000
SDRAM/refresh_req.Q to SDRAM/bank<1>.CE 0.000 10.000 -10.000
SDRAM/refresh_req.Q to SDRAM/can_start.D 0.000 10.000 -10.000
SDRAM/refresh_req.Q to SDRAM/command<2>.D 0.000 10.000 -10.000
SDRAM/refresh_req.Q to SDRAM/cycle_type.D 0.000 10.000 -10.000
SDRAM/refresh_req.Q to SDRAM/refresh_req.D 0.000 10.000 -10.000
SPEED_D.Q to CLOCKS/SPEED_D.D 0.000 10.000 -10.000
VMA.Q to DSACK1_SYNC.D 0.000 10.000 -10.000
rom_access.Q to SPEED_D.D 0.000 10.000 -10.000


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CLK100M to BERR 0.000 30.100 -30.100
CLK100M to DTACK 0.000 22.400 -22.400
CLK100M to BGACK30 0.000 21.400 -21.400
CLK100M to DSACK<1> 0.000 21.400 -21.400
A<24> to BERR 0.000 18.700 -18.700
A<25> to BERR 0.000 18.700 -18.700
A<26> to BERR 0.000 18.700 -18.700
AS30 to BERR 0.000 18.700 -18.700
CLK100M to AS 0.000 14.500 -14.500
CLK100M to CIIN 0.000 14.500 -14.500
CLK100M to LDS 0.000 14.500 -14.500
CLK100M to UDS 0.000 14.500 -14.500
CLK100M to VMA 0.000 14.500 -14.500
CLK100M to AVEC 0.000 13.700 -13.700
CLK100M to BG 0.000 13.700 -13.700
CLK100M to D<0> 0.000 13.700 -13.700
CLK100M to D<1> 0.000 13.700 -13.700
CLK100M to D<2> 0.000 13.700 -13.700
CLK100M to D<3> 0.000 13.700 -13.700
CLK100M to D<4> 0.000 13.700 -13.700
CLK100M to D<6> 0.000 13.700 -13.700
CLK100M to D<7> 0.000 13.700 -13.700
CLK100M to E 0.000 13.700 -13.700
CLK100M to IOR 0.000 13.700 -13.700
CLK100M to IOW 0.000 13.700 -13.700
CLK100M to STERM 0.000 13.700 -13.700
CLK100M to ARAM<0> 0.000 13.500 -13.500
CLK100M to ARAM<10> 0.000 13.500 -13.500
CLK100M to ARAM<11> 0.000 13.500 -13.500
CLK100M to ARAM<12> 0.000 13.500 -13.500
CLK100M to ARAM<1> 0.000 13.500 -13.500
CLK100M to ARAM<2> 0.000 13.500 -13.500
CLK100M to ARAM<3> 0.000 13.500 -13.500
CLK100M to ARAM<4> 0.000 13.500 -13.500
CLK100M to ARAM<5> 0.000 13.500 -13.500
CLK100M to ARAM<6> 0.000 13.500 -13.500
CLK100M to ARAM<7> 0.000 13.500 -13.500
CLK100M to ARAM<8> 0.000 13.500 -13.500
CLK100M to ARAM<9> 0.000 13.500 -13.500
CLK100M to BA<0> 0.000 13.500 -13.500
CLK100M to BA<1> 0.000 13.500 -13.500
CLK100M to CAS 0.000 13.500 -13.500
CLK100M to CBACK 0.000 13.500 -13.500
CLK100M to DQM<0> 0.000 13.500 -13.500
CLK100M to DQM<1> 0.000 13.500 -13.500
CLK100M to DQM<2> 0.000 13.500 -13.500
CLK100M to DQM<3> 0.000 13.500 -13.500
CLK100M to RAMWE 0.000 13.500 -13.500
CLK100M to RAS 0.000 13.500 -13.500
A<0> to CIIN 0.000 11.000 -11.000
A<10> to CIIN 0.000 11.000 -11.000
A<11> to CIIN 0.000 11.000 -11.000
A<12> to CIIN 0.000 11.000 -11.000
A<13> to CIIN 0.000 11.000 -11.000
A<14> to CIIN 0.000 11.000 -11.000
A<15> to CIIN 0.000 11.000 -11.000
A<16> to BUSEN 0.000 11.000 -11.000
A<16> to CIIN 0.000 11.000 -11.000
A<17> to BUSEN 0.000 11.000 -11.000
A<17> to CIIN 0.000 11.000 -11.000
A<18> to BUSEN 0.000 11.000 -11.000
A<18> to CIIN 0.000 11.000 -11.000
A<19> to BUSEN 0.000 11.000 -11.000
A<19> to CIIN 0.000 11.000 -11.000
A<20> to BUSEN 0.000 11.000 -11.000
A<20> to CIIN 0.000 11.000 -11.000
A<21> to BUSEN 0.000 11.000 -11.000
A<21> to CIIN 0.000 11.000 -11.000
A<22> to BUSEN 0.000 11.000 -11.000
A<22> to CIIN 0.000 11.000 -11.000
A<23> to BUSEN 0.000 11.000 -11.000
A<23> to CIIN 0.000 11.000 -11.000
A<24> to BUSEN 0.000 11.000 -11.000
A<24> to CIIN 0.000 11.000 -11.000
A<25> to BUSEN 0.000 11.000 -11.000
A<25> to CIIN 0.000 11.000 -11.000
A<26> to BUSEN 0.000 11.000 -11.000
A<27> to BUSEN 0.000 11.000 -11.000
A<28> to BUSEN 0.000 11.000 -11.000
A<29> to BUSEN 0.000 11.000 -11.000
A<3> to CIIN 0.000 11.000 -11.000
A<4> to CIIN 0.000 11.000 -11.000
A<5> to CIIN 0.000 11.000 -11.000
A<6> to BUSEN 0.000 11.000 -11.000
A<6> to CIIN 0.000 11.000 -11.000
A<7> to BUSEN 0.000 11.000 -11.000
A<7> to CIIN 0.000 11.000 -11.000
A<8> to CIIN 0.000 11.000 -11.000
A<9> to CIIN 0.000 11.000 -11.000
BGACK to DTACK 0.000 11.000 -11.000
SIZ<0> to CIIN 0.000 11.000 -11.000
A<0> to DQM<0> 0.000 10.000 -10.000
A<0> to DQM<1> 0.000 10.000 -10.000
A<0> to DQM<2> 0.000 10.000 -10.000
A<0> to DQM<3> 0.000 10.000 -10.000
A<10> to TOSCE 0.000 10.000 -10.000
A<11> to TOSCE 0.000 10.000 -10.000
A<12> to TOSCE 0.000 10.000 -10.000
A<13> to TOSCE 0.000 10.000 -10.000
A<14> to TOSCE 0.000 10.000 -10.000
A<15> to TOSCE 0.000 10.000 -10.000
A<16> to IDECS<0> 0.000 10.000 -10.000
A<16> to IDECS<1> 0.000 10.000 -10.000
A<16> to TOSCE 0.000 10.000 -10.000
A<17> to IDECS<0> 0.000 10.000 -10.000
A<17> to IDECS<1> 0.000 10.000 -10.000
A<17> to TOSCE 0.000 10.000 -10.000
A<18> to IDECS<0> 0.000 10.000 -10.000
A<18> to IDECS<1> 0.000 10.000 -10.000
A<18> to TOSCE 0.000 10.000 -10.000
A<19> to IDECS<0> 0.000 10.000 -10.000
A<19> to IDECS<1> 0.000 10.000 -10.000
A<19> to TOSCE 0.000 10.000 -10.000
A<1> to DQM<0> 0.000 10.000 -10.000
A<1> to DQM<1> 0.000 10.000 -10.000
A<1> to DQM<2> 0.000 10.000 -10.000
A<1> to DQM<3> 0.000 10.000 -10.000
A<20> to IDECS<0> 0.000 10.000 -10.000
A<20> to IDECS<1> 0.000 10.000 -10.000
A<20> to TOSCE 0.000 10.000 -10.000
A<21> to IDECS<0> 0.000 10.000 -10.000
A<21> to IDECS<1> 0.000 10.000 -10.000
A<21> to TOSCE 0.000 10.000 -10.000
A<22> to IDECS<0> 0.000 10.000 -10.000
A<22> to IDECS<1> 0.000 10.000 -10.000
A<22> to TOSCE 0.000 10.000 -10.000
A<23> to IDECS<0> 0.000 10.000 -10.000
A<23> to IDECS<1> 0.000 10.000 -10.000
A<23> to TOSCE 0.000 10.000 -10.000
A<24> to IDECS<0> 0.000 10.000 -10.000
A<24> to IDECS<1> 0.000 10.000 -10.000
A<24> to TOSCE 0.000 10.000 -10.000
A<25> to IDECS<0> 0.000 10.000 -10.000
A<25> to IDECS<1> 0.000 10.000 -10.000
A<25> to TOSCE 0.000 10.000 -10.000
A<26> to CIIN 0.000 10.000 -10.000
A<26> to IDECS<0> 0.000 10.000 -10.000
A<26> to IDECS<1> 0.000 10.000 -10.000
A<26> to TOSCE 0.000 10.000 -10.000
A<27> to CIIN 0.000 10.000 -10.000
A<27> to IDECS<0> 0.000 10.000 -10.000
A<27> to IDECS<1> 0.000 10.000 -10.000
A<27> to TOSCE 0.000 10.000 -10.000
A<28> to CIIN 0.000 10.000 -10.000
A<28> to IDECS<0> 0.000 10.000 -10.000
A<28> to IDECS<1> 0.000 10.000 -10.000
A<28> to TOSCE 0.000 10.000 -10.000
A<29> to CIIN 0.000 10.000 -10.000
A<29> to IDECS<0> 0.000 10.000 -10.000
A<29> to IDECS<1> 0.000 10.000 -10.000
A<29> to TOSCE 0.000 10.000 -10.000
A<3> to TOSCE 0.000 10.000 -10.000
A<4> to TOSCE 0.000 10.000 -10.000
A<5> to IDECS<0> 0.000 10.000 -10.000
A<5> to IDECS<1> 0.000 10.000 -10.000
A<5> to TOSCE 0.000 10.000 -10.000
A<6> to IDECS<0> 0.000 10.000 -10.000
A<6> to IDECS<1> 0.000 10.000 -10.000
A<6> to TOSCE 0.000 10.000 -10.000
A<7> to IDECS<0> 0.000 10.000 -10.000
A<7> to IDECS<1> 0.000 10.000 -10.000
A<7> to TOSCE 0.000 10.000 -10.000
A<8> to TOSCE 0.000 10.000 -10.000
A<9> to TOSCE 0.000 10.000 -10.000
AS30 to BUSEN 0.000 10.000 -10.000
AS30 to CIIN 0.000 10.000 -10.000
BGACK to BGACK30 0.000 10.000 -10.000
BGACK to BUSEN 0.000 10.000 -10.000
BR to BR30 0.000 10.000 -10.000
CBREQ to CBACK 0.000 10.000 -10.000
CLK100M to CLKRAM 0.000 10.000 -10.000
RW30 to DQM<0> 0.000 10.000 -10.000
RW30 to DQM<1> 0.000 10.000 -10.000
RW30 to DQM<2> 0.000 10.000 -10.000
RW30 to DQM<3> 0.000 10.000 -10.000
RW30 to TOSCE 0.000 10.000 -10.000
SIZ<0> to DQM<0> 0.000 10.000 -10.000
SIZ<0> to DQM<1> 0.000 10.000 -10.000
SIZ<0> to DQM<2> 0.000 10.000 -10.000
SIZ<1> to DQM<0> 0.000 10.000 -10.000
SIZ<1> to DQM<1> 0.000 10.000 -10.000
SIZ<1> to DQM<2> 0.000 10.000 -10.000
CLK100M to CLKCPU 0.000 5.800 -5.800
CLK100M to RAMOE 0.000 5.800 -5.800


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
A<16> to SPEED_D.D 0.000 10.100 -10.100
A<17> to SPEED_D.D 0.000 10.100 -10.100
A<18> to SPEED_D.D 0.000 10.100 -10.100
A<19> to SPEED_D.D 0.000 10.100 -10.100
A<20> to SPEED_D.D 0.000 10.100 -10.100
A<21> to SPEED_D.D 0.000 10.100 -10.100
A<22> to SPEED_D.D 0.000 10.100 -10.100
A<23> to SPEED_D.D 0.000 10.100 -10.100
A<24> to SPEED_D.D 0.000 10.100 -10.100
A<25> to SPEED_D.D 0.000 10.100 -10.100
A<26> to SPEED_D.D 0.000 10.100 -10.100
A<27> to SPEED_D.D 0.000 10.100 -10.100
A<28> to SPEED_D.D 0.000 10.100 -10.100
A<29> to SPEED_D.D 0.000 10.100 -10.100
A<6> to SPEED_D.D 0.000 10.100 -10.100
A<7> to SPEED_D.D 0.000 10.100 -10.100
FC<2> to SPEED_D.D 0.000 10.100 -10.100
RESET to SPEED_D.D 0.000 10.100 -10.100
FC<0> to SPEED_D.D 0.000 9.700 -9.700
FC<1> to SPEED_D.D 0.000 9.700 -9.700
A<11> to SDRAM/address<0>.D 0.000 9.300 -9.300
A<12> to SDRAM/address<1>.D 0.000 9.300 -9.300
A<21> to SDRAM/address<10>.D 0.000 9.300 -9.300
A<3> to SDRAM/address<1>.D 0.000 9.300 -9.300
AS30 to SPEED_D.D 0.000 9.300 -9.300
DS30 to SDRAM/cycle<0>.D 0.000 9.300 -9.300
FC<0> to VMA.D 0.000 9.300 -9.300
FC<1> to VMA.D 0.000 9.300 -9.300
FC<2> to VMA.D 0.000 9.300 -9.300
RW30 to SDRAM/address<10>.D 0.000 9.300 -9.300
A<0> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<0> to LDS.D 0.000 8.300 -8.300
A<0> to UDS.D 0.000 8.300 -8.300
A<10> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<10> to SDRAM/address<8>.D 0.000 8.300 -8.300
A<10> to rom_access.D 0.000 8.300 -8.300
A<11> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<11> to rom_access.D 0.000 8.300 -8.300
A<12> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<12> to rom_access.D 0.000 8.300 -8.300
A<13> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<13> to SDRAM/address<2>.D 0.000 8.300 -8.300
A<13> to rom_access.D 0.000 8.300 -8.300
A<14> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<14> to SDRAM/address<3>.D 0.000 8.300 -8.300
A<14> to rom_access.D 0.000 8.300 -8.300
A<15> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<15> to SDRAM/address<4>.D 0.000 8.300 -8.300
A<15> to rom_access.D 0.000 8.300 -8.300
A<16> to ATA/ASDLY.D 0.000 8.300 -8.300
A<16> to AVEC.D 0.000 8.300 -8.300
A<16> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<16> to CPCS_INT.D 0.000 8.300 -8.300
A<16> to SDRAM/address<5>.D 0.000 8.300 -8.300
A<16> to rom_access.D 0.000 8.300 -8.300
A<17> to ATA/ASDLY.D 0.000 8.300 -8.300
A<17> to AVEC.D 0.000 8.300 -8.300
A<17> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<17> to CPCS_INT.D 0.000 8.300 -8.300
A<17> to SDRAM/address<6>.D 0.000 8.300 -8.300
A<17> to rom_access.D 0.000 8.300 -8.300
A<18> to ATA/ASDLY.D 0.000 8.300 -8.300
A<18> to AVEC.D 0.000 8.300 -8.300
A<18> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<18> to CPCS_INT.D 0.000 8.300 -8.300
A<18> to SDRAM/address<7>.D 0.000 8.300 -8.300
A<18> to rom_access.D 0.000 8.300 -8.300
A<19> to ATA/ASDLY.D 0.000 8.300 -8.300
A<19> to AVEC.D 0.000 8.300 -8.300
A<19> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<19> to CPCS_INT.D 0.000 8.300 -8.300
A<19> to SDRAM/address<8>.D 0.000 8.300 -8.300
A<19> to rom_access.D 0.000 8.300 -8.300
A<1> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<20> to ATA/ASDLY.D 0.000 8.300 -8.300
A<20> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<20> to SDRAM/address<9>.D 0.000 8.300 -8.300
A<20> to rom_access.D 0.000 8.300 -8.300
A<21> to ATA/ASDLY.D 0.000 8.300 -8.300
A<21> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<21> to rom_access.D 0.000 8.300 -8.300
A<22> to ATA/ASDLY.D 0.000 8.300 -8.300
A<22> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<22> to SDRAM/address<11>.D 0.000 8.300 -8.300
A<22> to rom_access.D 0.000 8.300 -8.300
A<23> to ATA/ASDLY.D 0.000 8.300 -8.300
A<23> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<23> to SDRAM/address<12>.D 0.000 8.300 -8.300
A<23> to rom_access.D 0.000 8.300 -8.300
A<24> to ATA/ASDLY.D 0.000 8.300 -8.300
A<24> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<24> to RAMOE.D 0.000 8.300 -8.300
A<24> to SDRAM/bank<0>.D 0.000 8.300 -8.300
A<24> to rom_access.D 0.000 8.300 -8.300
A<25> to ATA/ASDLY.D 0.000 8.300 -8.300
A<25> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<25> to RAMOE.D 0.000 8.300 -8.300
A<25> to SDRAM/bank<1>.D 0.000 8.300 -8.300
A<25> to rom_access.D 0.000 8.300 -8.300
A<26> to ATA/ASDLY.D 0.000 8.300 -8.300
A<26> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<26> to RAMOE.D 0.000 8.300 -8.300
A<26> to rom_access.D 0.000 8.300 -8.300
A<27> to ATA/ASDLY.D 0.000 8.300 -8.300
A<27> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<27> to RAMOE.D 0.000 8.300 -8.300
A<27> to rom_access.D 0.000 8.300 -8.300
A<28> to ATA/ASDLY.D 0.000 8.300 -8.300
A<28> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<28> to RAMOE.D 0.000 8.300 -8.300
A<28> to rom_access.D 0.000 8.300 -8.300
A<29> to ATA/ASDLY.D 0.000 8.300 -8.300
A<29> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<29> to RAMOE.D 0.000 8.300 -8.300
A<29> to rom_access.D 0.000 8.300 -8.300
A<2> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<2> to SDRAM/BURSTING.D 0.000 8.300 -8.300
A<2> to SDRAM/address<0>.D 0.000 8.300 -8.300
A<3> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<3> to SDRAM/BURSTING.D 0.000 8.300 -8.300
A<3> to rom_access.D 0.000 8.300 -8.300
A<4> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<4> to SDRAM/address<2>.D 0.000 8.300 -8.300
A<4> to rom_access.D 0.000 8.300 -8.300
A<5> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<5> to SDRAM/address<3>.D 0.000 8.300 -8.300
A<5> to rom_access.D 0.000 8.300 -8.300
A<6> to ATA/ASDLY.D 0.000 8.300 -8.300
A<6> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<6> to SDRAM/address<4>.D 0.000 8.300 -8.300
A<6> to rom_access.D 0.000 8.300 -8.300
A<7> to ATA/ASDLY.D 0.000 8.300 -8.300
A<7> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<7> to SDRAM/address<5>.D 0.000 8.300 -8.300
A<7> to rom_access.D 0.000 8.300 -8.300
A<8> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<8> to SDRAM/address<6>.D 0.000 8.300 -8.300
A<8> to rom_access.D 0.000 8.300 -8.300
A<9> to BUSEN_IRQ.D 0.000 8.300 -8.300
A<9> to SDRAM/address<7>.D 0.000 8.300 -8.300
A<9> to rom_access.D 0.000 8.300 -8.300
AS to BG.D 0.000 8.300 -8.300
AS30 to AS.D 0.000 8.300 -8.300
AS30 to BG.D 0.000 8.300 -8.300
AS30 to BUSEN_IRQ.D 0.000 8.300 -8.300
AS30 to RAMOE.D 0.000 8.300 -8.300
AS30 to SDRAM/BURSTING.D 0.000 8.300 -8.300
AS30 to SDRAM/bank<0>.CE 0.000 8.300 -8.300
AS30 to SDRAM/bank<1>.CE 0.000 8.300 -8.300
AS30 to SDRAM/can_start.D 0.000 8.300 -8.300
AS30 to SDRAM/command<2>.D 0.000 8.300 -8.300
AS30 to SDRAM/cycle<0>.D 0.000 8.300 -8.300
AS30 to SDRAM/cycle_type.D 0.000 8.300 -8.300
AS30 to rom_access.D 0.000 8.300 -8.300
BG30 to BG.D 0.000 8.300 -8.300
BGACK to BGACK_INT.D 0.000 8.300 -8.300
BGACK to HIGHZ.D 0.000 8.300 -8.300
CBREQ to SDRAM/BURSTING.D 0.000 8.300 -8.300
CLK7M_RAW to CLOCKS/CLK7M_D<0>.D 0.000 8.300 -8.300
D<0> to D<0>.D 0.000 8.300 -8.300
D<1> to D<1>.D 0.000 8.300 -8.300
D<2> to D<2>.D 0.000 8.300 -8.300
D<3> to D<3>.D 0.000 8.300 -8.300
D<4> to D<4>.D 0.000 8.300 -8.300
D<6> to D<6>.D 0.000 8.300 -8.300
D<7> to D<7>.D 0.000 8.300 -8.300
DS30 to LDS.D 0.000 8.300 -8.300
DS30 to SDRAM/BURSTING.D 0.000 8.300 -8.300
DS30 to SDRAM/bank<0>.CE 0.000 8.300 -8.300
DS30 to SDRAM/bank<1>.CE 0.000 8.300 -8.300
DS30 to SDRAM/can_start.D 0.000 8.300 -8.300
DS30 to SDRAM/command<2>.D 0.000 8.300 -8.300
DS30 to SDRAM/cycle_type.D 0.000 8.300 -8.300
DS30 to UDS.D 0.000 8.300 -8.300
DTACK to BG.D 0.000 8.300 -8.300
DTACK to DTACK_D.D 0.000 8.300 -8.300
FC<0> to AVEC.D 0.000 8.300 -8.300
FC<0> to CPCS_INT.D 0.000 8.300 -8.300
FC<1> to AVEC.D 0.000 8.300 -8.300
FC<1> to CPCS_INT.D 0.000 8.300 -8.300
FC<2> to AVEC.D 0.000 8.300 -8.300
FC<2> to CPCS_INT.D 0.000 8.300 -8.300
IDEINT to BUSEN_IRQ.D 0.000 8.300 -8.300
RESET to SDRAM/BCOUNT<0>.D 0.000 8.300 -8.300
RESET to SDRAM/BCOUNT<1>.D 0.000 8.300 -8.300
RESET to SDRAM/BURSTING.CE 0.000 8.300 -8.300
RESET to SDRAM/WAIT_BLOCK.CE 0.000 8.300 -8.300
RESET to SDRAM/can_start.D 0.000 8.300 -8.300
RW30 to BUSEN_IRQ.D 0.000 8.300 -8.300
RW30 to IOR.D 0.000 8.300 -8.300
RW30 to IOW.D 0.000 8.300 -8.300
RW30 to LDS.D 0.000 8.300 -8.300
RW30 to SDRAM/BURSTING.D 0.000 8.300 -8.300
RW30 to SDRAM/command<0>.D 0.000 8.300 -8.300
RW30 to SDRAM/command<1>.D 0.000 8.300 -8.300
RW30 to UDS.D 0.000 8.300 -8.300
RW30 to rom_access.D 0.000 8.300 -8.300
SIZ<0> to LDS.D 0.000 8.300 -8.300
SIZ<1> to LDS.D 0.000 8.300 -8.300
VPA to AVEC.D 0.000 8.300 -8.300
CLK7M_RAW to AS_RESYNC<0>.CLKF 0.000 6.200 -6.200
CLK7M_RAW to AS_RESYNC<1>.CLKF 0.000 6.200 -6.200
CLK7M_RAW to DTACK_RESYNC<0>.CLKF 0.000 6.200 -6.200
CLK100M to FCLK-IO_0 0.000 1.800 -1.800
CLK100M to FCLKIO_1 0.000 1.800 -1.800


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
CPCS_INT.Q to BERR 0.000 20.400 -20.400
HIGHZ.Q to AS 0.000 12.700 -12.700
HIGHZ.Q to LDS 0.000 12.700 -12.700
HIGHZ.Q to UDS 0.000 12.700 -12.700
HIGHZ.Q to VMA 0.000 12.700 -12.700
RAMOE.Q to CIIN 0.000 12.700 -12.700
dtack_delay1.Q to DTACK 0.000 12.700 -12.700
BGACK_INT.Q to BGACK30 0.000 11.700 -11.700
DSACK1_SYNC.Q to DSACK<1> 0.000 11.700 -11.700
DTACK_D.Q to DSACK<1> 0.000 11.700 -11.700
DTACK_IDE.Q to DSACK<1> 0.000 11.700 -11.700
RAMOE.Q to DQM<0> 0.000 11.700 -11.700
RAMOE.Q to DQM<1> 0.000 11.700 -11.700
RAMOE.Q to DQM<2> 0.000 11.700 -11.700
RAMOE.Q to DQM<3> 0.000 11.700 -11.700
SDRAM/BURSTING.Q to CBACK 0.000 11.700 -11.700
SDRAM/address<0>.Q to ARAM<0> 0.000 11.700 -11.700
SDRAM/address<10>.Q to ARAM<10> 0.000 11.700 -11.700
SDRAM/address<11>.Q to ARAM<11> 0.000 11.700 -11.700
SDRAM/address<12>.Q to ARAM<12> 0.000 11.700 -11.700
SDRAM/address<1>.Q to ARAM<1> 0.000 11.700 -11.700
SDRAM/address<2>.Q to ARAM<2> 0.000 11.700 -11.700
SDRAM/address<3>.Q to ARAM<3> 0.000 11.700 -11.700
SDRAM/address<4>.Q to ARAM<4> 0.000 11.700 -11.700
SDRAM/address<5>.Q to ARAM<5> 0.000 11.700 -11.700
SDRAM/address<6>.Q to ARAM<6> 0.000 11.700 -11.700
SDRAM/address<7>.Q to ARAM<7> 0.000 11.700 -11.700
SDRAM/address<8>.Q to ARAM<8> 0.000 11.700 -11.700
SDRAM/address<9>.Q to ARAM<9> 0.000 11.700 -11.700
SDRAM/bank<0>.Q to BA<0> 0.000 11.700 -11.700
SDRAM/bank<1>.Q to BA<1> 0.000 11.700 -11.700
SDRAM/command<0>.Q to RAMWE 0.000 11.700 -11.700
SDRAM/command<1>.Q to CAS 0.000 11.700 -11.700
SDRAM/command<2>.Q to RAS 0.000 11.700 -11.700
SDRAM/init_address<10>.Q to ARAM<10> 0.000 11.700 -11.700
SDRAM/init_address<5>.Q to ARAM<5> 0.000 11.700 -11.700
SDRAM/init_address<5>.Q to ARAM<9> 0.000 11.700 -11.700
SDRAM/init_command<0>.Q to RAMWE 0.000 11.700 -11.700
SDRAM/init_command<1>.Q to CAS 0.000 11.700 -11.700
SDRAM/init_command<2>.Q to RAS 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<0> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<10> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<11> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<12> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<1> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<2> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<3> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<4> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<5> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<6> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<7> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<8> 0.000 11.700 -11.700
SDRAM/ready.Q to ARAM<9> 0.000 11.700 -11.700
SDRAM/ready.Q to BA<0> 0.000 11.700 -11.700
SDRAM/ready.Q to BA<1> 0.000 11.700 -11.700
SDRAM/ready.Q to CAS 0.000 11.700 -11.700
SDRAM/ready.Q to RAMWE 0.000 11.700 -11.700
SDRAM/ready.Q to RAS 0.000 11.700 -11.700
AS.Q to AS 0.000 4.000 -4.000
AVEC.Q to AVEC 0.000 4.000 -4.000
BG.Q to BG 0.000 4.000 -4.000
CLKCPU.Q to CLKCPU 0.000 4.000 -4.000
D<0>.Q to D<0> 0.000 4.000 -4.000
D<1>.Q to D<1> 0.000 4.000 -4.000
D<2>.Q to D<2> 0.000 4.000 -4.000
D<3>.Q to D<3> 0.000 4.000 -4.000
D<4>.Q to D<4> 0.000 4.000 -4.000
D<6>.Q to D<6> 0.000 4.000 -4.000
D<7>.Q to D<7> 0.000 4.000 -4.000
E.Q to E 0.000 4.000 -4.000
IOR.Q to IOR 0.000 4.000 -4.000
IOW.Q to IOW 0.000 4.000 -4.000
LDS.Q to LDS 0.000 4.000 -4.000
RAMOE.Q to RAMOE 0.000 4.000 -4.000
STERM.Q to STERM 0.000 4.000 -4.000
UDS.Q to UDS 0.000 4.000 -4.000
VMA.Q to VMA 0.000 4.000 -4.000



Number of constraints not met: 4

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
CLKCPU_OBUF.Q 71.429 Limited by Clock Pulse Width for CLKCPU_OBUF.Q
CLK7M_RAW 71.429 Limited by Clock Pulse Width for CLK7M_RAW
CLK7M.Q 71.429 Limited by Clock Pulse Width for CLK7M.Q
CLK100M 90.909 Limited by Cycle Time for CLK100M

Setup/Hold Times for Clocks

Setup/Hold Times for Clock BUSEN_IRQ.CLKF
Source Pad Setup to clk (edge) Hold to clk (edge)

Setup/Hold Times for Clock CLKCPU.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
A<16> 0.400 3.100
A<17> 0.400 3.100
A<18> 0.400 3.100
A<19> 0.400 3.100
A<20> 0.400 3.100
A<21> 0.400 3.100
A<22> 0.400 3.100
A<23> 0.400 3.100
A<24> 0.400 3.100
A<25> 0.400 3.100
A<26> 0.400 3.100
A<27> 0.400 3.100
A<28> 0.400 3.100
A<29> 0.400 3.100
A<6> 0.400 3.100
A<7> 0.400 3.100
FC<0> 0.400 3.100
FC<1> 0.400 3.100
FC<2> 0.400 3.100
RW30 0.400 3.100
VPA 0.400 3.100

Setup/Hold Times for Clock CLK7M.Q
Source Pad Setup to clk (edge) Hold to clk (edge)
AS 0.400 3.100
AS30 0.400 3.100
BG30 0.400 3.100
BGACK 0.400 3.100
D<0> 0.400 3.100
D<1> 0.400 3.100
D<2> 0.400 3.100
D<3> 0.400 3.100
D<4> 0.400 3.100
D<6> 0.400 3.100
D<7> 0.400 3.100
DTACK 0.400 3.100
FC<0> 1.400 2.100
FC<1> 1.400 2.100
FC<2> 1.400 2.100

Setup/Hold Times for Clock CLK100M
Source Pad Setup to clk (edge) Hold to clk (edge)
A<0> 6.500 0.000
A<10> 6.500 0.000
A<11> 7.500 0.000
A<12> 7.500 0.000
A<13> 6.500 0.000
A<14> 6.500 0.000
A<15> 6.500 0.000
A<16> 8.300 0.000
A<17> 8.300 0.000
A<18> 8.300 0.000
A<19> 8.300 0.000
A<20> 8.300 0.000
A<21> 8.300 0.000
A<22> 8.300 0.000
A<23> 8.300 0.000
A<24> 8.300 0.000
A<25> 8.300 0.000
A<26> 8.300 0.000
A<27> 8.300 0.000
A<28> 8.300 0.000
A<29> 8.300 0.000
A<2> 6.500 0.000
A<3> 7.500 0.000
A<4> 6.500 0.000
A<5> 6.500 0.000
A<6> 8.300 0.000
A<7> 8.300 0.000
A<8> 6.500 0.000
A<9> 6.500 0.000
AS30 7.500 0.000
BGACK 6.500 0.000
CBREQ 6.500 0.000
CLK7M_RAW 6.500 0.000
DS30 7.500 0.000
DTACK 6.500 0.000
FC<0> 7.900 0.000
FC<1> 7.900 0.000
FC<2> 8.300 0.000
RESET 8.300 0.000
RW30 7.500 0.000
SIZ<0> 6.500 0.000
SIZ<1> 6.500 0.000


Clock to Pad Timing

Clock CLK100M to Pad
Destination Pad Clock (edge) to Pad
BERR 30.100
DTACK 22.400
BGACK30 21.400
DSACK<1> 21.400
AS 14.500
CIIN 14.500
LDS 14.500
UDS 14.500
VMA 14.500
AVEC 13.700
BG 13.700
D<0> 13.700
D<1> 13.700
D<2> 13.700
D<3> 13.700
D<4> 13.700
D<6> 13.700
D<7> 13.700
E 13.700
IOR 13.700
IOW 13.700
STERM 13.700
ARAM<0> 13.500
ARAM<10> 13.500
ARAM<11> 13.500
ARAM<12> 13.500
ARAM<1> 13.500
ARAM<2> 13.500
ARAM<3> 13.500
ARAM<4> 13.500
ARAM<5> 13.500
ARAM<6> 13.500
ARAM<7> 13.500
ARAM<8> 13.500
ARAM<9> 13.500
BA<0> 13.500
BA<1> 13.500
CAS 13.500
CBACK 13.500
DQM<0> 13.500
DQM<1> 13.500
DQM<2> 13.500
DQM<3> 13.500
RAMWE 13.500
RAS 13.500
CLKCPU 5.800
RAMOE 5.800


Clock to Setup Times for Clocks

Clock to Setup for clock CLKCPU.Q
Source Destination Delay
ATA/ASDLY.Q ATA/ASDLY2.D 10.000
ATA/ASDLY.Q IOR.D 10.000
ATA/ASDLY2.Q DTACK_IDE.D 10.000
ATA/ASDLY2.Q IOW.D 10.000

Clock to Setup for clock CLK7M_RAW
Source Destination Delay
AS_RESYNC<0>.Q AS_RESYNC<1>.D 10.000

Clock to Setup for clock CLK7M.Q
Source Destination Delay
M6800BUS/Q<0>.Q VMA.D 11.000
M6800BUS/Q<1>.Q VMA.D 11.000
M6800BUS/Q<2>.Q VMA.D 11.000
M6800BUS/Q<3>.Q VMA.D 11.000
VMA.Q VMA.D 11.000
DSACK1_SYNC.Q DSACK1_SYNC.D 10.000
E.Q E.D 10.000
M6800BUS/Q<0>.Q DSACK1_SYNC.D 10.000
M6800BUS/Q<0>.Q E.D 10.000
M6800BUS/Q<0>.Q M6800BUS/Q<1>.D 10.000
M6800BUS/Q<0>.Q M6800BUS/Q<2>.D 10.000
M6800BUS/Q<0>.Q M6800BUS/Q<3>.D 10.000
M6800BUS/Q<1>.Q DSACK1_SYNC.D 10.000
M6800BUS/Q<1>.Q E.D 10.000
M6800BUS/Q<1>.Q M6800BUS/Q<1>.D 10.000
M6800BUS/Q<1>.Q M6800BUS/Q<2>.D 10.000
M6800BUS/Q<1>.Q M6800BUS/Q<3>.D 10.000
M6800BUS/Q<2>.Q DSACK1_SYNC.D 10.000
M6800BUS/Q<2>.Q E.D 10.000
M6800BUS/Q<2>.Q M6800BUS/Q<1>.D 10.000
M6800BUS/Q<2>.Q M6800BUS/Q<3>.D 10.000
M6800BUS/Q<3>.Q DSACK1_SYNC.D 10.000
M6800BUS/Q<3>.Q E.D 10.000
M6800BUS/Q<3>.Q M6800BUS/Q<1>.D 10.000
M6800BUS/Q<3>.Q M6800BUS/Q<3>.D 10.000
VMA.Q DSACK1_SYNC.D 10.000

Clock to Setup for clock CLK100M
Source Destination Delay
SDRAM/BCOUNT<0>.Q SDRAM/address<10>.D 11.000
SDRAM/BCOUNT<1>.Q SDRAM/address<10>.D 11.000
SDRAM/BCOUNT<1>.Q SDRAM/cycle<2>.D 11.000
SDRAM/BURSTING.Q SDRAM/address<10>.D 11.000
SDRAM/BURSTING.Q SDRAM/address<1>.D 11.000
SDRAM/BURSTING.Q SDRAM/cycle<2>.D 11.000
SDRAM/address<0>.Q SDRAM/address<0>.D 11.000
SDRAM/address<10>.Q SDRAM/address<10>.D 11.000
SDRAM/address<1>.Q SDRAM/address<1>.D 11.000
SDRAM/can_start.Q SDRAM/address<0>.D 11.000
SDRAM/can_start.Q SDRAM/address<10>.D 11.000
SDRAM/can_start.Q SDRAM/address<1>.D 11.000
SDRAM/cycle<0>.Q SDRAM/address<0>.D 11.000
SDRAM/cycle<0>.Q SDRAM/address<10>.D 11.000
SDRAM/cycle<0>.Q SDRAM/address<1>.D 11.000
SDRAM/cycle<0>.Q SDRAM/cycle<0>.D 11.000
SDRAM/cycle<0>.Q SDRAM/cycle<2>.D 11.000
SDRAM/cycle<1>.Q SDRAM/address<0>.D 11.000
SDRAM/cycle<1>.Q SDRAM/address<10>.D 11.000
SDRAM/cycle<1>.Q SDRAM/address<1>.D 11.000
SDRAM/cycle<1>.Q SDRAM/cycle<0>.D 11.000
SDRAM/cycle<1>.Q SDRAM/cycle<2>.D 11.000
SDRAM/cycle<2>.Q SDRAM/address<0>.D 11.000
SDRAM/cycle<2>.Q SDRAM/address<10>.D 11.000
SDRAM/cycle<2>.Q SDRAM/address<1>.D 11.000
SDRAM/cycle<2>.Q SDRAM/cycle<0>.D 11.000
SDRAM/cycle<3>.Q SDRAM/address<0>.D 11.000
SDRAM/cycle<3>.Q SDRAM/address<10>.D 11.000
SDRAM/cycle<3>.Q SDRAM/address<1>.D 11.000
SDRAM/cycle<3>.Q SDRAM/cycle<0>.D 11.000
SDRAM/cycle_type.Q SDRAM/address<10>.D 11.000
SDRAM/cycle_type.Q SDRAM/address<1>.D 11.000
SDRAM/ready.Q SDRAM/address<0>.D 11.000
SDRAM/ready.Q SDRAM/address<10>.D 11.000
SDRAM/ready.Q SDRAM/address<1>.D 11.000
SDRAM/refresh_req.Q SDRAM/cycle<0>.D 11.000
CLK7M.Q CLKCPU.D 10.000
CLKCPU.Q CLKCPU.D 10.000
CLOCKS/CLK7M_D<0>.Q CLOCKS/CLK7M_D<0>.D 10.000
CLOCKS/CLK7M_D<0>.Q CLOCKS/CLK7M_D<1>.D 10.000
CLOCKS/CLK7M_D<1>.Q CLOCKS/CLK7M_D<0>.D 10.000
CLOCKS/CLK7M_D<1>.Q CLOCKS/CLK7M_D<2>.D 10.000
CLOCKS/CLK7M_D<2>.Q CLOCKS/CLK7M_D<0>.D 10.000
CLOCKS/CLK7M_D<2>.Q CLOCKS/CLK7M_D<3>.D 10.000
CLOCKS/CLK7M_D<3>.Q CLK7M.D 10.000
CLOCKS/SPEED_D.Q CLKCPU.D 10.000
RAMOE.Q SDRAM/BURSTING.D 10.000
RAMOE.Q SDRAM/bank<0>.CE 10.000
RAMOE.Q SDRAM/bank<1>.CE 10.000
RAMOE.Q SDRAM/can_start.D 10.000
RAMOE.Q SDRAM/command<2>.D 10.000
RAMOE.Q SDRAM/cycle<0>.D 10.000
RAMOE.Q SDRAM/cycle_type.D 10.000
SDRAM/BCOUNT<0>.Q SDRAM/BCOUNT<0>.D 10.000
SDRAM/BCOUNT<0>.Q SDRAM/BCOUNT<1>.D 10.000
SDRAM/BCOUNT<0>.Q SDRAM/address<0>.D 10.000
SDRAM/BCOUNT<0>.Q SDRAM/cycle<2>.D 10.000
SDRAM/BCOUNT<1>.Q SDRAM/BCOUNT<1>.D 10.000
SDRAM/BCOUNT<1>.Q SDRAM/address<1>.D 10.000
SDRAM/BURSTING.Q SDRAM/address<0>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<10>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<11>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<1>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<2>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<3>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<4>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<5>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<6>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<7>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<8>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/INIT/COUNTER<9>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<0>.Q SDRAM/ready.CE 10.000
SDRAM/INIT/COUNTER<10>.Q SDRAM/INIT/COUNTER<11>.D 10.000
SDRAM/INIT/COUNTER<10>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<10>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<10>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<10>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<10>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<10>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<10>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<10>.Q SDRAM/refresh.D 10.000
SDRAM/INIT/COUNTER<11>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<11>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<11>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<11>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<11>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<11>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<11>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<11>.Q SDRAM/ready.D 10.000
SDRAM/INIT/COUNTER<12>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<12>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<12>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<12>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<12>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<12>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<12>.Q SDRAM/ready.D 10.000
SDRAM/INIT/COUNTER<13>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<13>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<13>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<13>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<13>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<13>.Q SDRAM/ready.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<10>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<11>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<2>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<3>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<4>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<5>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<6>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<7>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<8>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/INIT/COUNTER<9>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<1>.Q SDRAM/ready.CE 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/INIT/COUNTER<10>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/INIT/COUNTER<11>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/INIT/COUNTER<3>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/INIT/COUNTER<4>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/INIT/COUNTER<5>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/INIT/COUNTER<6>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/INIT/COUNTER<7>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/INIT/COUNTER<8>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/INIT/COUNTER<9>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<2>.Q SDRAM/ready.CE 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/INIT/COUNTER<10>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/INIT/COUNTER<11>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/INIT/COUNTER<4>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/INIT/COUNTER<5>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/INIT/COUNTER<6>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/INIT/COUNTER<7>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/INIT/COUNTER<8>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/INIT/COUNTER<9>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<3>.Q SDRAM/ready.CE 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/INIT/COUNTER<10>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/INIT/COUNTER<11>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/INIT/COUNTER<5>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/INIT/COUNTER<6>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/INIT/COUNTER<7>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/INIT/COUNTER<8>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/INIT/COUNTER<9>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<4>.Q SDRAM/ready.CE 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/INIT/COUNTER<10>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/INIT/COUNTER<11>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/INIT/COUNTER<6>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/INIT/COUNTER<7>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/INIT/COUNTER<8>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/INIT/COUNTER<9>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<5>.Q SDRAM/ready.CE 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/INIT/COUNTER<10>.D 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/INIT/COUNTER<11>.D 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/INIT/COUNTER<7>.D 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/INIT/COUNTER<8>.D 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/INIT/COUNTER<9>.D 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<6>.Q SDRAM/ready.CE 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/INIT/COUNTER<10>.D 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/INIT/COUNTER<11>.D 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/INIT/COUNTER<8>.D 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/INIT/COUNTER<9>.D 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<7>.Q SDRAM/ready.CE 10.000
SDRAM/INIT/COUNTER<8>.Q SDRAM/INIT/COUNTER<10>.D 10.000
SDRAM/INIT/COUNTER<8>.Q SDRAM/INIT/COUNTER<11>.D 10.000
SDRAM/INIT/COUNTER<8>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<8>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<8>.Q SDRAM/INIT/COUNTER<9>.D 10.000
SDRAM/INIT/COUNTER<8>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<8>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<8>.Q SDRAM/init_command<2>.D 10.000
SDRAM/INIT/COUNTER<9>.Q SDRAM/INIT/COUNTER<10>.D 10.000
SDRAM/INIT/COUNTER<9>.Q SDRAM/INIT/COUNTER<11>.D 10.000
SDRAM/INIT/COUNTER<9>.Q SDRAM/INIT/COUNTER<12>.D 10.000
SDRAM/INIT/COUNTER<9>.Q SDRAM/INIT/COUNTER<13>.D 10.000
SDRAM/INIT/COUNTER<9>.Q SDRAM/init_address<10>.D 10.000
SDRAM/INIT/COUNTER<9>.Q SDRAM/init_address<5>.CE 10.000
SDRAM/INIT/COUNTER<9>.Q SDRAM/init_command<0>.D 10.000
SDRAM/INIT/COUNTER<9>.Q SDRAM/init_command<1>.D 10.000
SDRAM/INIT/COUNTER<9>.Q SDRAM/init_command<2>.D 10.000
SDRAM/WAIT_BLOCK.Q SDRAM/WAIT_BLOCK.D 10.000
SDRAM/address<11>.Q SDRAM/address<11>.D 10.000
SDRAM/address<12>.Q SDRAM/address<12>.D 10.000
SDRAM/address<2>.Q SDRAM/address<2>.D 10.000
SDRAM/address<3>.Q SDRAM/address<3>.D 10.000
SDRAM/address<4>.Q SDRAM/address<4>.D 10.000
SDRAM/address<5>.Q SDRAM/address<5>.D 10.000
SDRAM/address<6>.Q SDRAM/address<6>.D 10.000
SDRAM/address<7>.Q SDRAM/address<7>.D 10.000
SDRAM/address<8>.Q SDRAM/address<8>.D 10.000
SDRAM/address<9>.Q SDRAM/address<9>.D 10.000
SDRAM/can_start.Q SDRAM/BURSTING.D 10.000
SDRAM/can_start.Q SDRAM/address<11>.D 10.000
SDRAM/can_start.Q SDRAM/address<12>.D 10.000
SDRAM/can_start.Q SDRAM/address<2>.D 10.000
SDRAM/can_start.Q SDRAM/address<3>.D 10.000
SDRAM/can_start.Q SDRAM/address<4>.D 10.000
SDRAM/can_start.Q SDRAM/address<5>.D 10.000
SDRAM/can_start.Q SDRAM/address<6>.D 10.000
SDRAM/can_start.Q SDRAM/address<7>.D 10.000
SDRAM/can_start.Q SDRAM/address<8>.D 10.000
SDRAM/can_start.Q SDRAM/address<9>.D 10.000
SDRAM/can_start.Q SDRAM/bank<0>.CE 10.000
SDRAM/can_start.Q SDRAM/bank<1>.CE 10.000
SDRAM/can_start.Q SDRAM/can_start.D 10.000
SDRAM/can_start.Q SDRAM/command<2>.D 10.000
SDRAM/can_start.Q SDRAM/cycle<0>.D 10.000
SDRAM/can_start.Q SDRAM/cycle_type.D 10.000
SDRAM/cycle<0>.Q SDRAM/BCOUNT<0>.D 10.000
SDRAM/cycle<0>.Q SDRAM/BCOUNT<1>.D 10.000
SDRAM/cycle<0>.Q SDRAM/BURSTING.CE 10.000
SDRAM/cycle<0>.Q SDRAM/WAIT_BLOCK.D 10.000
SDRAM/cycle<0>.Q SDRAM/address<11>.D 10.000
SDRAM/cycle<0>.Q SDRAM/address<12>.D 10.000
SDRAM/cycle<0>.Q SDRAM/address<2>.D 10.000
SDRAM/cycle<0>.Q SDRAM/address<3>.D 10.000
SDRAM/cycle<0>.Q SDRAM/address<4>.D 10.000
SDRAM/cycle<0>.Q SDRAM/address<5>.D 10.000
SDRAM/cycle<0>.Q SDRAM/address<6>.D 10.000
SDRAM/cycle<0>.Q SDRAM/address<7>.D 10.000
SDRAM/cycle<0>.Q SDRAM/address<8>.D 10.000
SDRAM/cycle<0>.Q SDRAM/address<9>.D 10.000
SDRAM/cycle<0>.Q SDRAM/bank<0>.CE 10.000
SDRAM/cycle<0>.Q SDRAM/bank<1>.CE 10.000
SDRAM/cycle<0>.Q SDRAM/can_start.D 10.000
SDRAM/cycle<0>.Q SDRAM/command<0>.D 10.000
SDRAM/cycle<0>.Q SDRAM/command<1>.D 10.000
SDRAM/cycle<0>.Q SDRAM/command<2>.D 10.000
SDRAM/cycle<0>.Q SDRAM/cycle<1>.D 10.000
SDRAM/cycle<0>.Q SDRAM/cycle<3>.D 10.000
SDRAM/cycle<0>.Q SDRAM/cycle_type.D 10.000
SDRAM/cycle<0>.Q SDRAM/refresh_req.D 10.000
SDRAM/cycle<1>.Q SDRAM/BCOUNT<0>.D 10.000
SDRAM/cycle<1>.Q SDRAM/BCOUNT<1>.D 10.000
SDRAM/cycle<1>.Q SDRAM/BURSTING.CE 10.000
SDRAM/cycle<1>.Q SDRAM/WAIT_BLOCK.D 10.000
SDRAM/cycle<1>.Q SDRAM/address<11>.D 10.000
SDRAM/cycle<1>.Q SDRAM/address<12>.D 10.000
SDRAM/cycle<1>.Q SDRAM/address<2>.D 10.000
SDRAM/cycle<1>.Q SDRAM/address<3>.D 10.000
SDRAM/cycle<1>.Q SDRAM/address<4>.D 10.000
SDRAM/cycle<1>.Q SDRAM/address<5>.D 10.000
SDRAM/cycle<1>.Q SDRAM/address<6>.D 10.000
SDRAM/cycle<1>.Q SDRAM/address<7>.D 10.000
SDRAM/cycle<1>.Q SDRAM/address<8>.D 10.000
SDRAM/cycle<1>.Q SDRAM/address<9>.D 10.000
SDRAM/cycle<1>.Q SDRAM/bank<0>.CE 10.000
SDRAM/cycle<1>.Q SDRAM/bank<1>.CE 10.000
SDRAM/cycle<1>.Q SDRAM/can_start.D 10.000
SDRAM/cycle<1>.Q SDRAM/command<0>.D 10.000
SDRAM/cycle<1>.Q SDRAM/command<1>.D 10.000
SDRAM/cycle<1>.Q SDRAM/command<2>.D 10.000
SDRAM/cycle<1>.Q SDRAM/cycle<3>.D 10.000
SDRAM/cycle<1>.Q SDRAM/cycle_type.D 10.000
SDRAM/cycle<1>.Q SDRAM/refresh_req.D 10.000
SDRAM/cycle<2>.Q SDRAM/BCOUNT<0>.D 10.000
SDRAM/cycle<2>.Q SDRAM/BCOUNT<1>.D 10.000
SDRAM/cycle<2>.Q SDRAM/BURSTING.CE 10.000
SDRAM/cycle<2>.Q SDRAM/WAIT_BLOCK.D 10.000
SDRAM/cycle<2>.Q SDRAM/address<11>.D 10.000
SDRAM/cycle<2>.Q SDRAM/address<12>.D 10.000
SDRAM/cycle<2>.Q SDRAM/address<2>.D 10.000
SDRAM/cycle<2>.Q SDRAM/address<3>.D 10.000
SDRAM/cycle<2>.Q SDRAM/address<4>.D 10.000
SDRAM/cycle<2>.Q SDRAM/address<5>.D 10.000
SDRAM/cycle<2>.Q SDRAM/address<6>.D 10.000
SDRAM/cycle<2>.Q SDRAM/address<7>.D 10.000
SDRAM/cycle<2>.Q SDRAM/address<8>.D 10.000
SDRAM/cycle<2>.Q SDRAM/address<9>.D 10.000
SDRAM/cycle<2>.Q SDRAM/bank<0>.CE 10.000
SDRAM/cycle<2>.Q SDRAM/bank<1>.CE 10.000
SDRAM/cycle<2>.Q SDRAM/can_start.D 10.000
SDRAM/cycle<2>.Q SDRAM/command<0>.D 10.000
SDRAM/cycle<2>.Q SDRAM/command<1>.D 10.000
SDRAM/cycle<2>.Q SDRAM/command<2>.D 10.000
SDRAM/cycle<2>.Q SDRAM/cycle<2>.D 10.000
SDRAM/cycle<2>.Q SDRAM/cycle<3>.D 10.000
SDRAM/cycle<2>.Q SDRAM/cycle_type.D 10.000
SDRAM/cycle<2>.Q SDRAM/refresh_req.D 10.000
SDRAM/cycle<3>.Q SDRAM/BCOUNT<0>.D 10.000
SDRAM/cycle<3>.Q SDRAM/BCOUNT<1>.D 10.000
SDRAM/cycle<3>.Q SDRAM/BURSTING.CE 10.000
SDRAM/cycle<3>.Q SDRAM/WAIT_BLOCK.D 10.000
SDRAM/cycle<3>.Q SDRAM/address<11>.D 10.000
SDRAM/cycle<3>.Q SDRAM/address<12>.D 10.000
SDRAM/cycle<3>.Q SDRAM/address<2>.D 10.000
SDRAM/cycle<3>.Q SDRAM/address<3>.D 10.000
SDRAM/cycle<3>.Q SDRAM/address<4>.D 10.000
SDRAM/cycle<3>.Q SDRAM/address<5>.D 10.000
SDRAM/cycle<3>.Q SDRAM/address<6>.D 10.000
SDRAM/cycle<3>.Q SDRAM/address<7>.D 10.000
SDRAM/cycle<3>.Q SDRAM/address<8>.D 10.000
SDRAM/cycle<3>.Q SDRAM/address<9>.D 10.000
SDRAM/cycle<3>.Q SDRAM/bank<0>.CE 10.000
SDRAM/cycle<3>.Q SDRAM/bank<1>.CE 10.000
SDRAM/cycle<3>.Q SDRAM/can_start.D 10.000
SDRAM/cycle<3>.Q SDRAM/command<0>.D 10.000
SDRAM/cycle<3>.Q SDRAM/command<1>.D 10.000
SDRAM/cycle<3>.Q SDRAM/command<2>.D 10.000
SDRAM/cycle<3>.Q SDRAM/cycle<2>.D 10.000
SDRAM/cycle<3>.Q SDRAM/cycle_type.D 10.000
SDRAM/cycle<3>.Q SDRAM/refresh_req.D 10.000
SDRAM/cycle_type.Q SDRAM/BCOUNT<0>.D 10.000
SDRAM/cycle_type.Q SDRAM/BCOUNT<1>.D 10.000
SDRAM/cycle_type.Q SDRAM/WAIT_BLOCK.D 10.000
SDRAM/cycle_type.Q SDRAM/address<0>.D 10.000
SDRAM/cycle_type.Q SDRAM/address<11>.D 10.000
SDRAM/cycle_type.Q SDRAM/address<12>.D 10.000
SDRAM/cycle_type.Q SDRAM/address<2>.D 10.000
SDRAM/cycle_type.Q SDRAM/address<3>.D 10.000
SDRAM/cycle_type.Q SDRAM/address<4>.D 10.000
SDRAM/cycle_type.Q SDRAM/address<5>.D 10.000
SDRAM/cycle_type.Q SDRAM/address<6>.D 10.000
SDRAM/cycle_type.Q SDRAM/address<7>.D 10.000
SDRAM/cycle_type.Q SDRAM/address<8>.D 10.000
SDRAM/cycle_type.Q SDRAM/address<9>.D 10.000
SDRAM/cycle_type.Q SDRAM/command<0>.D 10.000
SDRAM/cycle_type.Q SDRAM/command<1>.D 10.000
SDRAM/cycle_type.Q SDRAM/command<2>.D 10.000
SDRAM/cycle_type.Q SDRAM/cycle<2>.D 10.000
SDRAM/cycle_type.Q SDRAM/cycle_type.D 10.000
SDRAM/cycle_type.Q SDRAM/refresh_req.D 10.000
SDRAM/init_address<10>.Q SDRAM/init_address<10>.D 10.000
SDRAM/ready.Q SDRAM/BURSTING.D 10.000
SDRAM/ready.Q SDRAM/address<11>.D 10.000
SDRAM/ready.Q SDRAM/address<12>.D 10.000
SDRAM/ready.Q SDRAM/address<2>.D 10.000
SDRAM/ready.Q SDRAM/address<3>.D 10.000
SDRAM/ready.Q SDRAM/address<4>.D 10.000
SDRAM/ready.Q SDRAM/address<5>.D 10.000
SDRAM/ready.Q SDRAM/address<6>.D 10.000
SDRAM/ready.Q SDRAM/address<7>.D 10.000
SDRAM/ready.Q SDRAM/address<8>.D 10.000
SDRAM/ready.Q SDRAM/address<9>.D 10.000
SDRAM/ready.Q SDRAM/bank<0>.CE 10.000
SDRAM/ready.Q SDRAM/bank<1>.CE 10.000
SDRAM/ready.Q SDRAM/can_start.D 10.000
SDRAM/ready.Q SDRAM/command<2>.D 10.000
SDRAM/ready.Q SDRAM/cycle<0>.D 10.000
SDRAM/ready.Q SDRAM/cycle_type.D 10.000
SDRAM/ready.Q SDRAM/init_address<10>.D 10.000
SDRAM/ready.Q SDRAM/init_address<5>.CE 10.000
SDRAM/ready.Q SDRAM/init_command<0>.D 10.000
SDRAM/ready.Q SDRAM/init_command<1>.D 10.000
SDRAM/ready.Q SDRAM/init_command<2>.D 10.000
SDRAM/ready.Q SDRAM/ready.CE 10.000
SDRAM/ready.Q SDRAM/refresh.D 10.000
SDRAM/refresh.Q SDRAM/refresh_d.D 10.000
SDRAM/refresh.Q SDRAM/refresh_req.D 10.000
SDRAM/refresh_d.Q SDRAM/refresh_req.D 10.000
SDRAM/refresh_req.Q SDRAM/BURSTING.D 10.000
SDRAM/refresh_req.Q SDRAM/bank<0>.CE 10.000
SDRAM/refresh_req.Q SDRAM/bank<1>.CE 10.000
SDRAM/refresh_req.Q SDRAM/can_start.D 10.000
SDRAM/refresh_req.Q SDRAM/command<2>.D 10.000
SDRAM/refresh_req.Q SDRAM/cycle_type.D 10.000
SDRAM/refresh_req.Q SDRAM/refresh_req.D 10.000
SPEED_D.Q CLOCKS/SPEED_D.D 10.000
rom_access.Q SPEED_D.D 10.000


Pad to Pad List

Source Pad Destination Pad Delay
A<24> BERR 18.700
A<25> BERR 18.700
A<26> BERR 18.700
AS30 BERR 18.700
A<0> CIIN 11.000
A<10> CIIN 11.000
A<11> CIIN 11.000
A<12> CIIN 11.000
A<13> CIIN 11.000
A<14> CIIN 11.000
A<15> CIIN 11.000
A<16> BUSEN 11.000
A<16> CIIN 11.000
A<17> BUSEN 11.000
A<17> CIIN 11.000
A<18> BUSEN 11.000
A<18> CIIN 11.000
A<19> BUSEN 11.000
A<19> CIIN 11.000
A<20> BUSEN 11.000
A<20> CIIN 11.000
A<21> BUSEN 11.000
A<21> CIIN 11.000
A<22> BUSEN 11.000
A<22> CIIN 11.000
A<23> BUSEN 11.000
A<23> CIIN 11.000
A<24> BUSEN 11.000
A<24> CIIN 11.000
A<25> BUSEN 11.000
A<25> CIIN 11.000
A<26> BUSEN 11.000
A<27> BUSEN 11.000
A<28> BUSEN 11.000
A<29> BUSEN 11.000
A<3> CIIN 11.000
A<4> CIIN 11.000
A<5> CIIN 11.000
A<6> BUSEN 11.000
A<6> CIIN 11.000
A<7> BUSEN 11.000
A<7> CIIN 11.000
A<8> CIIN 11.000
A<9> CIIN 11.000
BGACK DTACK 11.000
SIZ<0> CIIN 11.000
A<0> DQM<0> 10.000
A<0> DQM<1> 10.000
A<0> DQM<2> 10.000
A<0> DQM<3> 10.000
A<10> TOSCE 10.000
A<11> TOSCE 10.000
A<12> TOSCE 10.000
A<13> TOSCE 10.000
A<14> TOSCE 10.000
A<15> TOSCE 10.000
A<16> IDECS<0> 10.000
A<16> IDECS<1> 10.000
A<16> TOSCE 10.000
A<17> IDECS<0> 10.000
A<17> IDECS<1> 10.000
A<17> TOSCE 10.000
A<18> IDECS<0> 10.000
A<18> IDECS<1> 10.000
A<18> TOSCE 10.000
A<19> IDECS<0> 10.000
A<19> IDECS<1> 10.000
A<19> TOSCE 10.000
A<1> DQM<0> 10.000
A<1> DQM<1> 10.000
A<1> DQM<2> 10.000
A<1> DQM<3> 10.000
A<20> IDECS<0> 10.000
A<20> IDECS<1> 10.000
A<20> TOSCE 10.000
A<21> IDECS<0> 10.000
A<21> IDECS<1> 10.000
A<21> TOSCE 10.000
A<22> IDECS<0> 10.000
A<22> IDECS<1> 10.000
A<22> TOSCE 10.000
A<23> IDECS<0> 10.000
A<23> IDECS<1> 10.000
A<23> TOSCE 10.000
A<24> IDECS<0> 10.000
A<24> IDECS<1> 10.000
A<24> TOSCE 10.000
A<25> IDECS<0> 10.000
A<25> IDECS<1> 10.000
A<25> TOSCE 10.000
A<26> CIIN 10.000
A<26> IDECS<0> 10.000
A<26> IDECS<1> 10.000
A<26> TOSCE 10.000
A<27> CIIN 10.000
A<27> IDECS<0> 10.000
A<27> IDECS<1> 10.000
A<27> TOSCE 10.000
A<28> CIIN 10.000
A<28> IDECS<0> 10.000
A<28> IDECS<1> 10.000
A<28> TOSCE 10.000
A<29> CIIN 10.000
A<29> IDECS<0> 10.000
A<29> IDECS<1> 10.000
A<29> TOSCE 10.000
A<3> TOSCE 10.000
A<4> TOSCE 10.000
A<5> IDECS<0> 10.000
A<5> IDECS<1> 10.000
A<5> TOSCE 10.000
A<6> IDECS<0> 10.000
A<6> IDECS<1> 10.000
A<6> TOSCE 10.000
A<7> IDECS<0> 10.000
A<7> IDECS<1> 10.000
A<7> TOSCE 10.000
A<8> TOSCE 10.000
A<9> TOSCE 10.000
AS30 BUSEN 10.000
AS30 CIIN 10.000
BGACK BGACK30 10.000
BGACK BUSEN 10.000
BR BR30 10.000
CBREQ CBACK 10.000
CLK100M CLKRAM 10.000
RW30 DQM<0> 10.000
RW30 DQM<1> 10.000
RW30 DQM<2> 10.000
RW30 DQM<3> 10.000
RW30 TOSCE 10.000
SIZ<0> DQM<0> 10.000
SIZ<0> DQM<1> 10.000
SIZ<0> DQM<2> 10.000
SIZ<1> DQM<0> 10.000
SIZ<1> DQM<1> 10.000
SIZ<1> DQM<2> 10.000


Number of paths analyzed: 919
Number of Timing errors: 919
Analysis Completed: Mon Mar 17 19:34:16 2025